PWM CONTROLLER. UC2825A-Q1 Datasheet

UC2825A-Q1 Datasheet PDF


Part Number

UC2825A-Q1

Description

HIGH-SPEED PWM CONTROLLER

Manufacture

etcTI

Total Page 20 Pages
Datasheet
Download UC2825A-Q1 Datasheet


UC2825A-Q1
www.ti.com
HIGH-SPEED PWM CONTROLLER
UC2825A-Q1
SLUS781 – SEPTEMBER 2007
FEATURES
1
Qualified for Automotive Applications
Improved Version of the UC3825 PWM
Compatible With Voltage-Mode or
Current-Mode Control Methods
Practical Operation at Switching Frequencies
to 1 MHz
50-ns Propagation Delay to Output
High-Current Dual Totem-Pole Outputs:
2 A (Peak)
Trimmed Oscillator Discharge Current
Low 100-μA Startup Current
Pulse-by-Pulse Current-Limiting Comparator
Latched Overcurrent Comparator With
Full-Cycle Restart
DESCRIPTION
The UC2825A pulse-width modulation (PWM)
controller is an improved versions of the standard
UC3825. Performance enhancements have been
made to several of the circuit blocks. Error amplifier
gain bandwidth product is 12 MHz, while input offset
voltage is 2 mV. Current limit threshold is specified to
a tolerance of 5%. Oscillator discharge current is
specified at 10 mA for accurate dead-time control.
Frequency accuracy is improved to 6%. Startup
supply current, typically 100 μA, is ideal for off-line
applications. The output drivers are redesigned to
actively sink current during undervoltage lockout
(UVLO) at no expense to the startup current
specification. In addition, each output is capable of
2-A peak currents during transitions.
BLOCK DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated

UC2825A-Q1
UC2825A-Q1
SLUS781 – SEPTEMBER 2007
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Functional improvements have also been implemented. The shutdown comparator is now a high-speed
overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full
discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the
low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that
the fault frequency does not exceed the designed soft start period. The CLOCK pin has become CLK/LEB. This
pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for
easier interfacing.
The UC2825A has dual alternating outputs and the same pin configuration of the UC3825. "A" version parts have
UVLO thresholds identical to the original UC3825.
See the application report, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers
(SLUA125) for detailed technical and application information.
ORDERING INFORMATION(1)
TJ
–40°C to 125°C
MAXIMUM
DUTY CYCLE
<50%
UVLO
9.2 V/8.4 V
PACKAGE (2)
SOIC – DW
Reel of 2000
ORDERABLE PART
NUMBER
UC2825AQDWRQ1
TOP-SIDE
MARKING
UC2825AQDW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
PIN ASSIGNMENTS
DW PACKAGE
(TOP VIEW)
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
1
2
3
4
5
6
7
8
16 VREF
15 VCC
14 OUTB
13 VC
12 PGND
11 OUTA
10 GND
9 ILIM
2 Submit Documentation Feedback
Copyright © 2007, Texas Instruments Incorporated





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