UCC27223
SLUS558 − DECEMBER 2003
HIGHĆEFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER WITH ENABLE
FEATURES
D Maximizes ...
UCC27223
SLUS558 − DECEMBER 2003
HIGHĆEFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER WITH ENABLE
FEATURES
D Maximizes Efficiency by Minimizing
Body-Diode Conduction and Reverse Recovery Losses
D Transparent Synchronous Buck Gate Drive
Operation From the Single Ended PWM Input Signal
D 12-V or 5-V Input Operation D 3.3-V Input Operation With Availability of
12-V Bus Bias
D High-Side and Low-Side ±3-A Dual Drivers D On-Board 6.5-V Gate Drive Regulator D ±3-A TrueDrive Gate Drives for High
Current Delivery at
MOSFET Miller Thresholds
D Automatically Adjusts for Changing
Operating Conditions
D Thermally Enhanced 14-Pin PowerPAD
HTSSOP Package Minimizes Board Area and Junction Temperature Rise
FUNCTIONAL APPLICATION DIAGRAM
APPLICATIONS
D Multiphase Converters in Combination With
the TPS40090
D Non-Isolated 3.3-V, 5-V and 12-V Input
dc-to-dc Converters for Processor Power, General Computer, Telecom and Datacom Applications
DESCRIPTION
The UCC27223 is a high-speed synchronous buck drivers for today’s high-efficiency, lower-output
voltage designs. Using Predictive Gate Drivet (PGD) control technology, these drivers reduce diode conduction and reverse recovery losses in the synchronous rectifier
MOSFET(s).
The UCC27223 includes an enable pin that controls the operation of both outputs. A logic latch is also included to keep both outputs low until the first PWM input pulse comes in. The RDS(on) of the SR pull-down sourcing device is also minimized for higher frequency operations....