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UPD411A-1 Datasheet

Part Number UPD411A-1
Manufacturers NEC
Logo NEC
Description 4096-BIT DYNAMIC RAMS
Datasheet UPD411A-1 DatasheetUPD411A-1 Datasheet (PDF)

NEe Microcomputers, Inc. NEe Jl.PD411A Jl.PD411A-1 Jl.PD411A-2 DESCR IPTION 4096 BIT DYNAMIC RAMS The ,uPD411A Famify consists of four 4096 words by 1 bit dynamic N-channel MOS RAMs. They are designed for memory applications where very low cost and large bit storage are important design objectives. The ,uPD411 A Family is designed using dynamic circuitry which reduces the standby power dissipation. Reading information from the memory is non·destructive. Refreshing is easily II accomplishe.

  UPD411A-1   UPD411A-1






Part Number UPD411A-2
Manufacturers NEC
Logo NEC
Description 4096-BIT DYNAMIC RAMS
Datasheet UPD411A-1 DatasheetUPD411A-2 Datasheet (PDF)

NEe Microcomputers, Inc. NEe Jl.PD411A Jl.PD411A-1 Jl.PD411A-2 DESCR IPTION 4096 BIT DYNAMIC RAMS The ,uPD411A Famify consists of four 4096 words by 1 bit dynamic N-channel MOS RAMs. They are designed for memory applications where very low cost and large bit storage are important design objectives. The ,uPD411 A Family is designed using dynamic circuitry which reduces the standby power dissipation. Reading information from the memory is non·destructive. Refreshing is easily II accomplishe.

  UPD411A-1   UPD411A-1







4096-BIT DYNAMIC RAMS

NEe Microcomputers, Inc. NEe Jl.PD411A Jl.PD411A-1 Jl.PD411A-2 DESCR IPTION 4096 BIT DYNAMIC RAMS The ,uPD411A Famify consists of four 4096 words by 1 bit dynamic N-channel MOS RAMs. They are designed for memory applications where very low cost and large bit storage are important design objectives. The ,uPD411 A Family is designed using dynamic circuitry which reduces the standby power dissipation. Reading information from the memory is non·destructive. Refreshing is easily II accomplished by performing one read cycle on each of the 64 row addresses. Each row address must be refreshed every two milliseconds. The memory is refreshed whether Chip Select is a logic high or a logic low. FEATURES • Low Standby Power • 4096 words x 1 bit Organization • A single low·capacitance high level clock input with solid ±1 volt margins. • Inactive Power 0.7 mW (Typ.) • Power Supply +12, +5, -5V • Easy System Interface • TTL Compatible (Except CE) • Address Registers on th.


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