W83627DHG

www.DataSheet4U.com W83627DHG WINBOND LPC I/O Note: This document is for UBC, UBE and UBF version except specified descriptions Date : April 10, 2007 Version : 1.4 W83627DHG Data Sheet Revision History PAGES DATES VERSION WEB VERSION MAIN CONTENTS 1 2 N.A. N.A. 12/15/2005 02/22/2006 0.1 0.2 N.A. N.A. 1. 1. 1. 2. 3. 4. 5. 6. 7. 1. 2. 3. 4. First published version. Add descriptions of the registers, functions,, AC/DC timing, and top marking Revise Table 8.1 and the timing chart of section 10.3.1 Add registers for AMDSI at LDB, CRF5h,CRF6h and F7h(Bank1) Swap LDB, CRF2h bit 0 and bit 1. Modify the default values for LDA, CRFEh Modify the descriptions of LD9, CR30h bit 0 and CRF7h bit 4. Remove LDA, CRE9h bit4 ~ 3 Swap LDC, CRE0h bit3~0 and CRE5h bit7~4 Add FDC, UART, Parallel Port and KBC interface descriptions Remove all the descriptions about AMDSI Modify the diagrams and descriptions for Current Mode Add two control bits for the selections of SYSFANOUT and CPUFANOUT0 output type at CR[24h] Remove the description of the internal pulled-up resistor of Parallel Port Modify the definitions of edge/level and enable/disable debounce circuit of GP30, GP31 and GP35 Modify the descriptions of LD7, CRF7h and LD9, CRE6h ~ CRE9h Remove the remaining descriptions about AMDSI in datasheet ver.0.4 Add a note for Index# of FDC Interface and pin 83(GP42) of Serial Port & Infrared Port Interface in Pin Description Reserve the bit 7 of LD0, CRF0h Modify the descriptions of TRAK0#, W...