SDRAM. WED3DL3216V Datasheet

WED3DL3216V Datasheet PDF

Part WED3DL3216V
Description 16Mx32 SDRAM
Feature WED3DL3216V; www.datasheet4u.com White Electronic Designs 16Mx32 SDRAM FEATURES 40% Space Savings vs. Monolithic.
Manufacture White Electronic Designs
Datasheet
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WED3DL3216V
www.datasheet4u.com
White Electronic Designs
WED3DL3216V
16Mx32 SDRAM
FEATURES
40% Space Savings vs. Monolithic Solution
Reduced System Inductance and Capacitance
3.3V Operating Supply Voltage
Fully Synchronous to Positive Clock Edge
Clock Frequencies of 100MHz - 133MHz
Burst Operation
• Sequential or Interleave
• Burst Length = Programmable 1, 2, 4, 8
or Full Page
• Burst Read and Write
• Multiple Burst Read and Single Write
Data Mask Control Per Byte
Auto and Self Refresh
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
119 Pin BGA, 17mm x 23mm
DESCRIPTION
The WED3DL3216V is an 16Mx32 Synchronous DRAM
configured as 4x4Mx32. The SDRAM BGA is constructed
with two 16Mx16 SDRAM die mounted on a multi-layer
laminate substrate and packaged in a 119 lead, 17mm
by 23mm, BGA.
The WED3DL3216V is available in clock speeds
of 133MHz, 125MHz, and 100MHz. The range of
operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
The package and design provides performance
enhancements via a 50% reduction in capacitance vs.
two monolithic devices. The design includes internal
ground and power planes which reduces inductance
on the ground and power pins allowing for improved
decoupling and a reduction in system noise.
PIN CONFIGURATION
(Top view)
123 4 5 67
A VCCQ NC
B NC NC
BA0 NC A10
A12 CAS# A11
A7 VCCQ A
NC NC B
C NC NC BA1 VCC A9 A8 NC C
D DQC NC VSS NC VSS NC DQB D
E DQC DQC VSS CE# VSS DQB DQB E
F VCCQ DQC VSS RAS# VSS DQB VCCQ F
G DQC DQC DQMC NC DQMB DQB DQB G
H DQC DQC VSS CKE VSS DQB DQB H
J VCCQ VCC NC VCC NC VCC VCCQ J
K DQD DQD VSS CK VSS DQA DQA K
L DQD DQD DQMD NC DQMA DQA DQA L
M VCCQ DQD VSS WE# VSS DQA VCCQ M
N DQD DQD VSS A1 VSS DQA DQA N
P DQD NC VSS A0 VSS NC DQA P
R NC A6 NC VCC NC A2 NC R
T NC NC A5 A4 A3 NC NC T
U VCCQ NC NC NC NC NC VCCQ U
123 4 5 67
PIN DESCRIPTION
A0 – A12 Address Bus
BA0-1 Bank Select Addresses
DQ Data Bus
CK Clock
CKE Clock Enable
DQM Data Input/Output Mask
RAS# Row Address Strobe
CAS# Column Address Strobe
CE# Chip Enable
VCC Power Supply pins, 3.3V
VCCQ Data Bus Power Supply pins,3.3V
VSS Ground pins
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com



WED3DL3216V
www.datasheet4u.com
White Electronic Designs
WED3DL3216V
ADDR0-12
BA0
BA1
DQMA
DQMB
CE#
RAS#
CAS#
WE#
CK
CKE
DQMC
DQMD
16MX32 SDRAM BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
DQ0-7 DQA
BA1 DQ8-15 DQB
LDQM#
UDQM#
CS#
RAS#
CAS#
WE#
CK
CKE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 DQ0-7 DQC
A10
A11
DQ8-15 DQD
A12
BA0
BA1
LDQM#
UDQM#
CS#
RAS#
CAS#
WE#
CK
CKE
DQ0-31
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com



WED3DL3216V
www.datasheet4u.com
White Electronic Designs
WED3DL3216V
Symbol
CK
CKE
CE#
RAS#, CAS#,
WE#
BA0, BA1
A0-12
DQ
Type
Input
Input
Input
Input
Input
Input
Input/Output
Signal
Pulse
Level
Pulse
Pulse
Level
Level
Level
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Polarity
Positive Edge
Active High
Active Low
Active Low
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode
CE# disable or enable device operation by masking or enabling all inputs except CK, CKE and
DQM.
When sampled at the positive rising edge of the clock, CAS#, RAS# and WE# define the
operation to be executed by the SDRAM
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-12 defines the row address (RA0-12) when sampled
at the rising clock edge.
During a Read or Write command cycle, A0-9 defines the column address (CA0-9) when
sampled at the rising edge of the clock. In addition to the row address, A10/AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high,
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10/AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the
state of BA0, BA1. If A10/AP is low, than BA0, BA1 is used to define which bank to precharge.
Data Input/Output are multiplexed on the same pins
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol Min Max Units
Power Supply Voltage
VCC/VCCQ -1.0 +4.6 V
Input Voltage
VIN -1.0 +4.6 V
Output Voltage
VOUT -1.0 +4.6 V
Operating Temperature
TOPR -0 +70 °C
Storage Temperature
TTSG -55 +125 °C
Power Dissipation
PD — 1.5 W
Short Circuit Output Current
IOS
— 50 mA
* Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






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