XC3S200A

0 Spartan-3A FPGA Family: Data Sheet DS529 December 18, 2018 0 0 Product Specification Module 1: Introduction and Ordering Information DS529 (v2.1) December 18, 2018 Introduction Features Architectural and Configuration Overview General I/O Capabilities Production Status Supported Packages and Package Marking Ordering Information Module 2: Spartan-3A FPGA Family: Functional Description DS529 (v2.1) December 18, 2018 The functionality of the Spartan®-3A FPGA family is described in the following documents. UG331: Spartan-3 Generation FPGA User Guide Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs) - Distributed RAM - SRL16 Shift Registers - Carry and Arithmetic Logic I/O Resources Embedded Multiplier Blocks Programmable Interconnect ISE® Design Tools and IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management UG332: Spartan-3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior Bitstream Sizes Detailed Descriptions by Mode - Master Serial Mode using Platform Flash PROM - Master SPI Mode using Commodity Serial Flash - Master BPI Mode using Commodity Parallel Flash - Slave Parallel (SelectMAP) using a Processor - Slave Serial using a Processor - JTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNA UG334: Spartan...