XC3SD3400A

1 Spartan-3A DSP FPGA Family Data Sheet DS610 October 4, 2010 Module 1: Introduction and Ordering Information DS610 (v3.0) October 4, 2010 Introduction Features Architectural Overview Configuration Overview General I/O Capabilities Supported Packages and Package Marking Ordering Information Module 2: Functional Description DS610 (v3.0) October 4, 2010 The functionality of the Spartan®-3A DSP FPGA family is described in the following documents. UG331: Spartan-3 Generation FPGA User Guide Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs) - Distributed RAM - SRL16 Shift Registers - Carry and Arithmetic Logic I/O Resources Programmable Interconnect ISE® Software Design Tools and IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power Management UG332: Spartan-3 Generation Configuration User Guide Configuration Overview Configuration Pins and Behavior Bitstream Sizes Detailed Descriptions by Mode - Master Serial Mode using Platform Flash PROM - Master SPI Mode using Commodity Serial Flash - Master BPI Mode using Commodity Parallel Flash - Slave Parallel (SelectMAP) using a Processor - Slave Serial using a Processor - JTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNA Product Specification UG431: XtremeDSP™ DSP48A for Spartan-3A DSP FPGAs User Guide DSP48A Slice...