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XCV600 Datasheet

Part Number XCV600
Manufacturers Xilinx
Logo Xilinx
Description Virtex Field Programmable Gate Array
Datasheet XCV600 DatasheetXCV600 Datasheet (PDF)

0 R Virtex™ 2.5 V www.DataSheet4U.com Field Programmable Gate Arrays 0 0 DS003-1 (v2.5 ) April 2, 2001 Product Specification Features • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant - Hot-swappable for Compact PCI Multi-standard SelectIO™ interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices Built-in clock-management circuitry - Four dedicated delay-lock.

  XCV600   XCV600






Part Number XCV600E
Manufacturers Xilinx
Logo Xilinx
Description 1.8V Field Programmable Gate Arrays
Datasheet XCV600 DatasheetXCV600E Datasheet (PDF)

— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — 0 R Virtex™-E 1.8 V Field Programmable Gate Arrays DS022-1 (v3.0) March 21, 2014 00 Features • Fast, High-Density 1.8 V FPGA Family - Densities from 58 k to 4 M system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz • Highly Flexible SelectI/O+™ Technology - Supports 20 high-performance interface standards - Up to 804 singled-ended I/Os or 344 differential I/O p.

  XCV600   XCV600







Virtex Field Programmable Gate Array

0 R Virtex™ 2.5 V www.DataSheet4U.com Field Programmable Gate Arrays 0 0 DS003-1 (v2.5 ) April 2, 2001 Product Specification Features • Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant - Hot-swappable for Compact PCI Multi-standard SelectIO™ interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs) for advanced clock control - Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets Hierarchical memory system - LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register - Configurable synchronous dual-ported 4k-bit RAMs - Fast interfaces to external high-performance RAMs Flexible architecture that balances speed and density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode • Supported by FPGA Foundation™ and Alliance Development Systems - Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager - Wide selection of PC and workstation platforms SRAM-based in-system configuration - Unlimited re-programmability - Four .


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