XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
AUG 2008 REV. V1.0.0
FEATURES • Performs clock and data re...
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
AUG 2008 REV. V1.0.0
FEATURES Performs clock and data recovery for selectable
data of 622.08 Mbps (STS-12/STM-4) or 155.52 Mbps (STS-3/STM-1) NRZ data
APPLICATIONS SONET/SDH-based Transmission Systems Add/Drop Multiplexers Cross Connect Equipment ATM and Multi-Service Switches, Routers and
Switch/Routers
Meets Telcordia, ANSI and ITU-T G.783 and G.825
SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications.
Lock output pin monitors data run length and
frequency drift from reference clock
Data is resampled at the output Active High Signal Detect (SIGD) LVPECL input Low jitter, high-speed outputs support LVPECL and
low-power LVDS termination
DSLAMS SONET/SDH Test Equipment DWDM Termination Equipment GENERAL DESCRIPTION
The XRT91L33 is a fully integrated multirate Clock and Data Recovery (CDR) device for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/ STM-1 applications. The device provides Clock and Data Recovery (CDR) function by synchronizing its on-chip
Voltage Controlled Oscillator (VCO) to the incoming serial scrambled non-return to zero (NRZ) data stream. Figure 1 shows the block diagram of the XRT91L33.
19.44 MHz reference frequency LVTTL input Low power: 215 mW typical 3.3V power supply 20-pin TSSOP package Requires one external capacitor PLL bypass operation facilitate...