ZL40241

Data Sheet ZL40241 Ten LVCMOS Output Low Additive Jitter Fanout Buffer Features 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal Ten 1.5V/1.8V/2.5V/3.3V LVCMOS outputs Supports frequencies from 0 to 200MHz Supports crystals from 8MHz to 60MHz Ultra-low additive jitter: 17fs (12kHz to 20MHz) Ultra-low noise floor of -170dBc/Hz Supports 2.5V or 3.3V power supplies Output to output skew of 30ps (typical) Input to output delay of 2ns (typical) Ordering Information ZL40241LDG1 ZL40241LDF1 32 Pin QFN Trays 32 pin QFN Tape and Reel Applications Package size: 5 x 5 mm -40C to +85C -40C to +85C General purpose clock distribution Low jitter clock trees Logic translation Clock and data signal restoration Wired and Wireless communications High performance microprocessor clock distribution Medical Imaging Test equipment OE SEL0 SEL1 IN0_p IN0_n IN1_p IN1_n XOUT XIN ZL40241 Synchronous OE 00 01 10 11 October 2018 © 2018 Microsemi Corporation Figure 1. Functional Block Diagram ZL40241 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 1 Table of Contents Data Sheet ZL40241 Features..................................................................................................................................... 1 Table of Contents ...............................................................