CY7C1380S Datasheet

CY7C1380S 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM

Functional Description The CY7C1380S/CY7C1382S SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock in.

Features

■ Supports bus operation up to 167 MHz
■ Available speed grade is 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3 V core power supply
■ 2.5 V or 3.3 V I/O power supply
■ Fast clock-to-output times
❐ 3.4 ns (for 167 MHz device)
■ Provides high-performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Single cycle chip deselect
■ CY7C1380S available in JEDEC-standard Pb-free 100-pin TQFP and.