The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetc.
CAS Latency and Frequency
CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR266 DDR333 -8 -7 -7F -6 100 133 133 133 125 143 143 166
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions .
Similar Product
No. | Part # | Manufacture | Description | Datasheet |
---|---|---|---|---|
1 | HYB25D256400B |
Infineon Technologies AG |
256 Mbit Double Data Rate SDRAM | |
2 | HYB25D256400BC |
Infineon |
256-Mbit Double Data Rate SDRAM | |
3 | HYB25D256400CC |
Infineon |
256 Mbit Double Data Rate SDRAM | |
4 | HYB25D256400CE |
Infineon |
256 Mbit Double Data Rate SDRAM | |
5 | HYB25D256400CF |
Infineon |
256 Mbit Double Data Rate SDRAM |