82433LX Datasheet

82433LX LOCAL BUS ACCELERATOR

2 1 Host Interface Signals 2 2 Main Memory (DRAM) Interface Signals 2 3 PCI Interface Signals 2 4 PCMC Interface Signals 2 5 Reset and Clock Signals 3 0 FUNCTIONAL DESCRIPTION 3 1 LBX Post and Prefetch Buffers 3 1 1 CPU-TO-MEMORY POSTED WRITE BUFFER 3 1 2 PCI-TO-MEMORY POSTED WRITE BUFFER 3 1 3 PCI.

Features

Byte Parity Support for the Host and Memory Buses Optional Parity Generation for Host to Memory Transfers Optional Parity Checking for the Secondary Cache Parity Checking for Host and PCI Memory Reads Parity Generation for PCI to Memory Writes 160-Pin QFP Package Y Y Y Y Y Y Y Y Y Two 82433LX or 82433NX Local Bus Accelerator (LBX) components provide a 64-bit data path between the host CPU Cache and main memory a 32-bit data path between the host CPU bus and PCI Local Bus and a 32-bit data path between the PCI Local Bus and main memory The dual-port architecture allows concurrent ope.