54ACT377 Datasheet

54ACT377 Octal D Flip-Flop

The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the .

Features

n ICC reduced by 50% Logic Symbols IEEE/IEC DS100290-1 DS100290-2 Pin Names D0
  –D7 CE Q0
  –Q7 CP Description Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100290 www.national.com Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100290-4 DS100290-3 Mode Select-Function Table Operating Mode CP Load ‘1’ Load ‘0’ Hold (Do Nothing) N N N Inputs.