UPA672T Datasheet

UPA672T N-CHANNEL MOS FET ARRAY

of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesa.

Features

• Two MOS FET circuits in package the same size as SC-70
• Automatic mounting supported 1.25 ±0.1 2.1 ±0.1 6 5 4 0 to 0.1 1 2 3 0.7 0.9 ±0.1 0.65 0.65 1.3 2.0 ±0.2 PIN CONNECTION 6 5 4 1 2 3 1. Source 1 (S1) 2. Gate 1 (G1) 3. Drain 2 (D2) 4. Source 2 (S2) 5. Gate 2 (G2) 6. Drain 1 (D1) Marking: MA ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C) PARAMETER Drain to Source Voltage Gate to Source Voltage Drain Current (DC) Drain Current (pulse) Total Power Dissipation Channel Temperature Storage Temperature SYMBOL VDSS VGSS ID(DC) ID(pulse) PT Tch Tstg PW ≤ 10 ms, Duty Cycle ≤ 50 % TEST CONDITIONS .