DDRII SDRAM. A3R1GE4EGF Datasheet

A3R1GE4EGF SDRAM. Datasheet pdf. Equivalent

Part A3R1GE4EGF
Description 1Gb DDRII SDRAM
Feature A3R1GE4EGF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specification A3R1GE4EGF Zentel Electronics C.
Manufacture Zentel
Datasheet
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A3R1GE4EGF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specif A3R1GE4EGF Datasheet
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A3R1GE4EGF
A3R1GE4EGF
1Gb DDRII Synchronous DRAM
1Gb DDRII SDRAM Specification
A3R1GE4EGF
Zentel Electronics Corp.
Revision 1.0
Apr., 2010



A3R1GE4EGF
Specifications
Density: 1G bits
Organization
8M words × 16 bits × 8 banks (A3R1GE4EGF)
Package
84-ball FBGA(μBGA) (A3R1GE4EGF)
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Data rate: 800Mbps/667Mbps (max.)
⎯ 800Μbps/667Mbps(max)
2KB page size (A3R1GE4EGF)
Row address: A0 to A12
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_18
Burst lengths (BL): 4, 8
Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
/CAS Latency (CL): 3, 4, 5, 6
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8μs at 0°C TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
A3R1GE4EGF
1Gb DDRII Synchronous DRAM
Features
Double-data-rate architecture; two data transfers per clock
cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS) is
transmitted/received with data for capturing data at the
receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
Revision 1.0
Zentel Electronics Corporation reserve the right to change products or specification without notice.
Page 1 / 76
Apr., 2010





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