EFFECT TRANSISTOR. NP50P04SLG Datasheet

NP50P04SLG TRANSISTOR. Datasheet pdf. Equivalent


Part NP50P04SLG
Description MOS FIELD EFFECT TRANSISTOR
Feature NP50P04SLG MOS FIELD EFFECT TRANSISTOR Preliminary Data Sheet R07DS0241EJ0100 Rev.1.00 Feb 09, 2011.
Manufacture Renesas
Datasheet
Download NP50P04SLG Datasheet


NP50P04SLG MOS FIELD EFFECT TRANSISTOR Preliminary Data She NP50P04SLG Datasheet
Recommendation Recommendation Datasheet NP50P04SLG Datasheet




NP50P04SLG
NP50P04SLG
MOS FIELD EFFECT TRANSISTOR
Preliminary Data Sheet
R07DS0241EJ0100
Rev.1.00
Feb 09, 2011
Description
The NP50P04SLG is P-channel MOS Field Effect Transistor designed for high current switching applications.
Features
Super low on-state resistance
RDS(on)1 = 9.6 mΩ MAX. (VGS = 10 V, ID = 25 A)
RDS(on)2 = 15 mΩ MAX. (VGS = 4.5 V, ID = 25 A)
Low input capacitance
Gate to Source ESD protection diode built-in
Ordering Information
Part No.
LEAD PLATING
PACKING
NP50P04SLG-E1-AY 1
NP50P04SLG-E2-AY 1
Pure Sn (Tin)
Tape 2500 p/reel
Note: 1. Pb-free (This product does not contain Pb in external electrode.)
Package
TO-252 (MP-3ZK)
Absolute Maximum Ratings (TA = 25°C)
Item
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) 1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
Storage Temperature
Single Avalanche Current 2
Single Avalanche Energy 2
Symbol
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
PT2
Tch
Tstg
IAS
EAS
Ratings
40
m20
m50
m150
84
1.2
175
55 to +175
37
136
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance ∗2
Rth(ch-C)
Rth(ch-A)
1.78 °C/W
125 °C/W
Notes: 1. PW 10 μs, Duty Cycle 1%
2. Starting Tch = 25°C, VDD = 20 V, RG = 25 Ω, VGS = 20 0 V
R07DS0241EJ0100 Rev.1.00
Feb 09, 2011
Page 1 of 6



NP50P04SLG
NP50P04SLG
Electrical Characteristics (TA = 25°C)
Item
Symbol Min
Zero Gate Voltage Drain Current IDSS
Gate Leakage Current
IGSS
Gate to Source Threshold
VGS(th)
1.0
Voltage
Forward Transfer Admittance 1 | yfs |
12
Drain to Source On-state
Resistance 1
RDS(on)1
RDS(on)2
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Turn-on Delay Time
td(on)
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
Gate to Source Charge
QGS
Gate to Drain Charge
Body Diode Forward Voltage 1
QGD
VF(S-D)
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Note: 1. Pulsed test PW 350 μs, Duty Cycle 2%
Typ
1.4
44
8.2
9.8
3800
740
500
11
15
250
150
100
13
30
0.96
50
63
Max
1
m10
2.5
9.6
15
5700
1120
905
24
39
505
380
150
1.5
Chapter Title
Unit
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = 40 V, VGS = 0 V
VGS = m20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 10 V, ID = 25 A
VGS = 10 V, ID = 25 A
VGS = 4.5 V, ID = 25 A
VDS = 10 V,
VGS = 0 V,
f = 1 MHz
VDD = 20 V, ID = 25 A,
VGS = 10 V,
RG = 0 Ω
VDD = 32 V,
VGS = 10 V,
ID = 50 A
IF = 50 A, VGS = 0 V
IF = 50 A, VGS = 0 V,
di/dt = 100 A/μs
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
VGS = 20 0 V
50 Ω
VDD
IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS()
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS()
VGS
Wave Form
0 10%
VDS()
90%
VDS
VDS
Wave Form 0
td(on)
VGS 90%
90%
10% 10%
tr td(off)
tf
ton toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
R07DS0241EJ0100 Rev.1.00
Feb 09, 2011
Page 2 of 6







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)