16-bit Microcontroller. MB96320 Datasheet

MB96320 Microcontroller. Datasheet pdf. Equivalent


Cypress Semiconductor MB96320
MB96320 Series
F2MC-16FX, 16-bit Microcontroller
MB96320 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The
CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new
16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the
same operation frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz
operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with
excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The
emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select
suitable operation frequencies for peripheral resources independent of the CPU speed.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-04584 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 25, 2016


MB96320 Datasheet
Recommendation MB96320 Datasheet
Part MB96320
Description 16-bit Microcontroller
Feature MB96320; MB96320 Series F2MC-16FX, 16-bit Microcontroller MB96320 series is based on Cypress advanced 16FX ar.
Manufacture Cypress Semiconductor
Datasheet
Download MB96320 Datasheet




Cypress Semiconductor MB96320
MB96320 Series
Features
Feature
Technology
CPU
System clock
On-chip voltage regulator
Low voltage reset
Code Security
Memory Patch Function
DMA
Interrupts
Timers
CAN
USART
I2C
Description
0.18m CMOS
F2MC-16FX CPU
Up to 56 MHz internal, 17.8 ns instruction cycle time
Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
addressing modes; barrel shift; variety of pointers)
8-byte instruction execution queue
Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available
On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator
depends on Q-factor).
Up to 56 MHz external clock
32-100 kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog
Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC
oscillator, independently for CPU and 2 clock domains of peripherals.
Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode)
Clock modulator
Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power
consumption figures
Reset is generated when supply voltage is below minimum.
Protects ROM content from unintended read-out
Replaces ROM content
Can also be used to implement embedded debug support
Automatic transfer function independent of CPU, can be assigned freely to resources
Fast Interrupt processing
8 programmable priority levels
Non-Maskable Interrupt (NMI)
Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
Watchdog Timer
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1 Mbit/s
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
Full duplex USARTs (SCI/LIN)
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
Up to 400 kbps
Master and Slave functionality, 8-bit and 10-bit addressing
Document Number: 002-04584 Rev. *A
Page 2 of 93



Cypress Semiconductor MB96320
MB96320 Series
Feature
Description
A/D converter
SAR-type
10-bit resolution
Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion
mode, activation by software, external trigger or reload timer
Reload Timers
16-bit wide
Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
Event count function
Free Running Timers
Signals an interrupt on
with 1, 1/21, 1/22, 1/23,
overflow, supports timer clear upon match with Output Compare
1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency
(0,
4),
Prescaler
Input Capture Units
16-bit wide
Signals an interrupt upon external event
Rising edge, falling edge or rising & falling edge sensitive
Output Compare Units
16-bit wide
Signals an interrupt when a match with 16-bit I/O Timer occurs
A pair of compare registers can be used to generate an output signal.
16-bit down counter, cycle and duty setting registers
Interrupt at trigger, counter borrow and/or duty match
Programmable Pulse Genera- PWM operation and one-shot operation
tor Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow
as clock input
Can be triggered by software or reload timer
Real Time Clock
Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the
RC oscillator
Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every half second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s clock
External Interrupts
Edge sensitive or level sensitive
Interrupt mask and pending bit per channel
Each available CAN channel RX has an external interrupt for wake-up
Selected USART channels SIN have an external interrupt for wake-up
Non Maskable Interrupt
Disabled after reset
Once enabled, can not be disabled other than by reset.
Level high or level low sensitive
Pin shared with external interrupt 0.
External bus interface
8-bit or 16-bit bidirectional data
Up to 24-bit addresses
6 chip select signals
Multiplexed address/data lines
Wait state request
External bus master possible
Timing programmable
Document Number: 002-04584 Rev. *A
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