Document
IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL
128K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
OCTOBER 2009
FEATURES • High-speed access time: 35ns, 45ns, 55ns • CMOS low power operation: 12 mW (typical) operating 4 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply: 1.65V--2.2V Vdd (62WV1288DALL) 2.3V--3.6V Vdd (62WV1288DBLL) • Fully static operation: no clock or refresh
required • Three state outputs • Industrial and automotive temperature support • Lead-free available
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS62/65WV1288DALL and IS62/65WV1288DBLL
are high-speed, 1M bit static RAMs organized as
128K words by 8 bits. It is fabricated using ISSI's high-
performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory.
The IS62/65WV1288DALL and IS62/65WV1288DBLL are packaged in the JEDEC standard 32-pin TSOP (TYPEI), sTSOP (TYPEI), SOP, and 36-pin mini BGA.
A0-A16
VDD GND
I/O0-I/O7
DECODER
I/O DATA CIRCUIT
CS2 CS1
OE WE
CONTROL CIRCUIT
128K x 8 MEMORY ARRAY
COLUMN I/O
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A 09/29/09
1
IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL
PIN CONFIGURATION 36-pin mini BGA (B) (6mm x 8mm)
1 23 45 6
A A0 A1 CS2 A3 A6 A8
B I/O4 A2 WE A4 A7 I/O0
C I/O5
NC A5
I/O1
D GND
VDD
E VDD
GND
F I/O6
NC NC
I/O2
G I/O7 OE CS1 A16 A15 I/O3
H A9 A10 A11 A12 A13 A14
PIN DESCRIPTIONS
A0-A16
CS1
CS2
OE
WE
I/O0-I/O7
NC
Vdd
GND
Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground
2
32-pin TSOP (TYPE I) (T), 32-pin sTSOP (TYPE I) (H)
A11 1 A9 2 A8 3 A13 4 WE 5 CS2 6 A15 7 VDD 8 NC 9 A16 10 A14 11 A12 12 A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CS1 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3
32-pin SOP (Q)
NC A16 A14 A12
A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 VDD 31 A15 30 CS2 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS1 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A 09/29/09
IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL
TRUTH TABLE
Mode
Not Selected (Power-down) Output Disabled Read Write
WE CS1 CS2 OE
X H X X X X L X H L H H H L H L L L H X
I/O Operation
Vdd Current
High-Z Isb1, Isb2
High-Z
Isb1, Isb2
High-Z Icc
Dout
Icc
Din
Icc
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
Vterm Terminal Voltage with Respect to GND –0.5 to Vdd + 0.5 V
Vdd
Vdd Relates to GND
–0.3 to 4.0
V
Tstg
Storage Temperature
–65 to +150
°C
Pt
Power Dissipation
1.0 W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter
Conditions
Max.
Cin
Input Capacitance
Vin = 0V
6
CI/O
Input/Output Capacitance
Vout = 0V
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Unit pF pF
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A 09/29/09
3
IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL
AC TEST CONDITIONS
Parameter
Unit (2.3V-3.6V)
Unit (3.3V + 5%)
Input Pulse Level
0.4V to Vdd - 0.3V
0.4V to Vdd - 0.3V
Input Rise and Fall Times
1V/ ns
1V/ ns
Input and Output Timing
VDD /2
VDD + 0.05
and Reference Level (VRef) 2
Output Load
See Figures 1 and 2 See Figures 1 and 2
R1 ( Ω )
317 317
R2 ( Ω )
351 351
Vtm (V)
3.3V
3.3V
Unit (1.65V-2.2V) 0.4V to Vdd - 0.3V
1V/ ns 0.9V
See Figures 1 and 2 13500 10800 1.8V
AC TEST LOADS
VTM
R1
OUTPUT 30 pF
Including jig and scope
Figure 1.
R2
VTM
R1
OUTPUT 5 pF
Including jig and scope
Figure 2.
R2
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A 09/29/09
IS62WV1288DALL/DBLL IS65WV1288DALL/DBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
Symbol Parameter
Test Conditions
Min.
Voh
Outpu.