D Flip-Flops. 54LS175 Datasheet

54LS175 Flip-Flops. Datasheet pdf. Equivalent


National Semiconductor 54LS175
June 1989
54LS174 DM54LS174 DM74LS174
54LS175 DM54LS175 DM74LS175
Hex Quad D Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic All have a direct clear
input and the quad (175) versions feature complementary
outputs from each flip-flop
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse Clock triggering occurs at a particu-
lar voltage level and is not directly related to the transition
time of the positive-going pulse When the clock input is at
either the high or low level the D input signal has no effect
at the output
Features
Y LS174 contains six flip-flops with single-rail outputs
Y LS175 contains four flip-flops with double-rail outputs
Y Buffered clock and direct clear inputs
Y Individual data input to each flip-flop
Y Applications include
Buffer storage registers
Shift registers
Pattern generators
Y Typical clock frequency 40 MHz
Y Typical power dissipation per flip-flop 14 mW
Y Alternate Military Aerospace device (54LS174
54LS175) is available Contact a National Semiconduc-
tor Sales Office Distributor for specifications
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL F 6404 – 1
Order Number 54LS174DMQB 54LS174FMQB
54LS174LMQB DM54LS174J
DM54LS174W DM74LS174M or DM74LS174N
See NS Package Number E20A J16A
M16A N16E or W16A
TL F 6404 – 2
Order Number 54LS175DMQB 54LS175FMQB
54LS175LMQB DM54LS175J
DM54LS175W DM74LS175M or DM74LS175N
See NS Package Number E20A J16A
M16A N16E or W16A
Function Table (Each Flip-Flop)
Clear
L
H
H
H
Inputs
Clock
X
u
u
L
D
X
H
L
X
Outputs
QQ
LH
HL
LH
Q0 Q0
H e High Level (steady state)
L e Low Level (steady state)
X e Don’t Care
u e Transition from low to high level
Q0 e The level of Q before the indicated steady-state input conditions were
established
e LS175 only
C1995 National Semiconductor Corporation TL F 6404
RRD-B30M105 Printed in U S A


54LS175 Datasheet
Recommendation 54LS175 Datasheet
Part 54LS175
Description Hex/Quad D Flip-Flops
Feature 54LS175; 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear June 1989 .
Manufacture National Semiconductor
Datasheet
Download 54LS175 Datasheet




National Semiconductor 54LS175
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS and 54LS
b55 C to a125 C
DM74LS
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
fCLK
fCLK
tW
tSU
tH
tREL
TA
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
Clock Frequency (Note 2)
Pulse Width
(Note 6)
Clock
Clear
Data Setup Time (Note 6)
Data Hold Time (Note 6)
Clear Release Time (Note 6)
Free Air Operating Temperature
Min
45
2
0
0
20
20
20
0
25
b55
DM54LS174
Nom
5
Max
55
07
b0 4
4
30
25
125
DM74LS174
Min Nom Max
4 75 5
5 25
2
08
b0 4
8
0 30
0 25
20
20
20
0
25
0 70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
C
’LS174 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 3)
Max
VI
Input Clamp Voltage
VCC e Min II e b18 mA
b1 5
VOH
High Level Output
Voltage
VCC e Min IOH e Max
VIL e Max VIH e Min
DM54
DM74
25
27
34
34
VOL Low Level Output
Voltage
VCC e Min IOL e Max
VIL e Max VIH e Min
DM54
DM74
0 25 0 4
0 35 0 5
IOL e 4 mA VCC e Min
DM74
II
Input Current Max
VCC e Max VI e 7V
Input Voltage
0 25 0 4
01
IIH
High Level Input Current
VCC e Max VI e 2 7V
IIL Low Level Input
Current
VCC e Max
VI e 0 4V
Clock
Clear
20
b0 4
b0 4
Data
b0 36
IOS Short Circuit
Output Current
VCC e Max
(Note 4)
DM54
DM74
b20
b20
b100
b100
ICC Supply Current
VCC e Max (Note 5)
16 26
Note 1 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 2 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 3 All typicals are at VCC e 5V TA e 25 C
Note 4 Not more than one output should be shorted at a time and the duration should not exceed one second
Note 5 With all outputs open and 4 5V applied to all data and clear inputs ICC is measured after a momentary ground then 4 5V applied to the clock
Note 6 TA e 25 C and VCC e 5V
Units
V
V
V
mA
mA
mA
mA
mA
2



National Semiconductor 54LS175
’LS174 Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL e 2 kX
CL e 15 pF
CL e 50 pF
Min Max Min Max
fMAX
tPLH
Maximum Clock Frequency
Propagation Delay Time
Low to High Level Output
Clock to
Output
30 25
30 32
tPHL
Propagation Delay Time
High to Low Level Output
Clock to
Output
30 36
tPHL
Propagation Delay Time
High to Low Level Output
Clear to
Output
35 42
Recommended Operating Conditions
Symbol
Parameter
VCC Supply Voltage
VIH High Level Input Voltage
VIL Low Level Input Voltage
IOH High Level Output Current
IOL Low Level Output Current
fCLK
Clock Frequency (Note 1)
fCLK
Clock Frequency (Note 2)
tW Pulse Width
(Note 3)
Clock
Clear
tSU Data Setup Time (Note 3)
tH Data Hold Time (Note 3)
tREL
Clear Release Time (Note 3)
TA Free Air Operating Temperature
Note 1 CL e 15 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 2 CL e 50 pF RL e 2 kX TA e 25 C and VCC e 5V
Note 3 TA e 25 C and VCC e 5V
DM54LS175
Min Nom Max
45 5 55
2
07
b0 4
4
0 30
0 25
20
20
20
0
25
b55
125
DM74LS175
Min Nom Max
4 75 5
5 25
2
08
b0 4
8
0 30
0 25
20
20
20
0
25
0 70
Units
MHz
ns
ns
ns
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
C
3





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