SHIFT/STORAGE REGISTER. SN74LS323 Datasheet

SN74LS323 REGISTER. Datasheet pdf. Equivalent

Part SN74LS323
Description 8-BIT SHIFT/STORAGE REGISTER
Feature 8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS323 is an 8-Bit Universal Shift / S.
Manufacture Motorola
Datasheet
Download SN74LS323 Datasheet



SN74LS323
8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS
The SN54 / 74LS323 is an 8-Bit Universal Shift / Storage Register with
3-state outputs. Its function is similar to the SN54 / 74LS299 with the exception
of Synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin count. Separate inputs and outputs are provided
for flip-flops Q0 and Q7 to allow easy cascading.
Four operation modes are possible: hold (store), shift left, shift right, and
parallel load. All modes are activated on the LOW-to-HIGH transition of the
Clock.
Common I/O for Reduced Pin Count
Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store
Separate Continuous Inputs and Outputs from Q0 and Q7 Allow Easy
Cascading
Fully Synchronous Reset
3-State Outputs for Bus Oriented Applications
Input Clamp Diodes Limit High-Speed Termination Effects
ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC S1 DS7 Q7 I/O7 I/O5 I/O3 I/O1 CP DS0
20 19 18 17 16 15 14 13 12 11
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 5 6 7 8 9 10
S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 SR GND
SN54/74LS323
8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
20
1
20
1
20
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
PIN NAMES
CP
DS0
DS7
I/On
OE1, OE2
Q0, Q7
S0, S1
SR
Clock Pulse (active positive going edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3-State) (Note c)
3-State Output Enable (active LOW) Inputs
Serial Outputs (Note b)
Mode Select Inputs
Synchronous Reset (active LOW) Input
NOTES:
a) 1 TTL LOAD = 40 µA HIGH/1.6 mA LOW.
b) The output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial Temperature Ranges.
c) The output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial Temperature Ranges.
The output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial Temperature Ranges.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
65 (25) U.L.
0.5 U.L.
10 U.L.
1 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
15 (7.5) U.L.
0.25 U.L.
5 (2.5) U.L.
0.25 U.L.
FAST AND LS TTL DATA
5-1



SN74LS323
S1 19 S0 1
SN54 / 74LS323
LOGIC DIAGRAM
DS0 11
9
SR
12
CP
Q0 8
2
OE1
OE2 3
18
DS7
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
17
Q Q7
7 13 6
I/O0 I/O1
I/O2
14
I/O3
5
I/O4
15
I/O5
4
I/O6
16
I/O7
FUNCTIONAL DESCRIPTION
The logic diagram and truth table indicate the functional
characteristics of the SN54/74LS323 Universal Shift/Storage
Register. This device is similar in operation to the
SN54/74LS299 except for synchronous reset. A partial list of
the common features are described below:
1. They use eight D-type edge-triggered flip-flops that re-
spond only to the LOW-to-HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control (S0, S1) and data inputs (DS0, DS7, I/O0–I/O7) may
be stable at least a setup time prior to the positive transition
of the Clock Pulse.
2. When S0 = S1 = 1, I/O0–I/O7 are parallel inputs to flip-flops
Q0–Q7 respectively, and the outputs of Q0–Q7 are in the
high impedance state regardless of the state of OE1 or
OE2.
An important unique feature of the SN54/74LS323 is a fully
Synchronous Reset that requires only to be stable at least one
setup time prior to the positive transition of the Clock Pulse.
TRUTH TABLE
INPUTS
RESPONSE
SR S1 S0 OE1 OE2 CP DS0 DS7
LXXH X
LXX X H
LHH X X
X
X
X
X
Synchronous Reset; Q0 = Q7 = LOW
I/O voltage undetermined
XX
LLX L
LXL L
L
L
X X Synchronous Reset; Q0 = Q7 = LOW
X X I/O voltage LOW
HLHX X
HLH L L
D X Shift Right; D Q0; Q0 Q1; etc.
D X Shift Right; D Q0 & I/O0; Q0 Q1 & I/O1; etc.
HHL X X
HHL L L
X D Shift Left; D Q7; Q7 Q6; etc.
X D Shift Left; D Q7 & I/O7; Q7 Q6 & I/O6; etc.
HHH X X
X X Parallel Load I/On Qn
H L L H X X X X Hold; I/O Voltage Undetermined
HLL X HXX X
H L L L L X X X Hold; I/On = Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
FAST AND LS TTL DATA
5-2





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