Microcontroller. MPC5602D Datasheet

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MPC5602D Datasheet
Recommendation MPC5602D Datasheet
Part MPC5602D
Description Microcontroller
Feature MPC5602D; Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5602D Rev. 6, 01/2013 MPC56.
Manufacture Freescale Semiconductor
Datasheet
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Freescale Semiconductor MPC5602D
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5602D
Rev. 6, 01/2013
MPC5602D Microcontroller
Data Sheet
• Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with the Power Architecture®
embedded category
— Includes an instruction set enhancement
allowing variable length encoding (VLE) for
code size footprint reduction. With the optional
encoding of mixed 16-bit and 32-bit
instructions, it is possible to achieve significant
code size footprint reduction.
• Up to 256 KB on-chip Code Flash supported with
Flash controller and ECC
• 64 KB on-chip Data Flash with ECC
• Up to 16 KB on-chip SRAM with ECC
• Interrupt controller (INTC) with multiple interrupt
vectors, including 20 external interrupt sources and
18 external interrupt/wakeup sources
• Frequency modulated phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, Flash, or SRAM from multiple bus
masters
• Boot assist module (BAM) supports internal Flash
programming via a serial link (CAN or SCI)
• Timer supports input/output channels providing a
range of 16-bit input capture, output compare, and
pulse width modulation functions (eMIOS-lite)
• Up to 33 channel 12-bit analog-to-digital converter
(ADC)
• 2 serial peripheral interface (DSPI) modules
• 3 serial communication interface (LINFlex) modules
— LINFlex 1 and 2: Master capable
— LINFlex 0: Master capable and slave capable;
connected to eDMA
• 1 enhanced full CAN (FlexCAN) module with
configurable buffers
MPC5602D
100 LQFP
14 mm x 14 mm
64 LQFP
10 mm x 10 mm
• Up to 79 configurable general purpose pins
supporting input and output operations (package
dependent)
• Real Time Counter (RTC) with clock source from
128 kHz or 16 MHz internal RC oscillator
supporting autonomous wakeup with 1 ms
resolution with max timeout of 2 seconds
• Up to 4 periodic interrupt timers (PIT) with 32-bit
counter resolution
• 1 System Timer Module (STM)
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class 1 standard
• Device/board boundary Scan testing supported with
per Joint Test Action Group (JTAG) of IEEE (IEEE
1149.1)
• On-chip voltage regulator (VREG) for regulation of
input supply for all internal levels
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2009–2013. All rights reserved.



Freescale Semiconductor MPC5602D
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7
3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Pad configuration during reset phases . . . . . . . . . . . . . .9
3.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .21
4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . .22
4.3.2 NVUSRO[OSCILLATOR_MARGIN] field
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.3 NVUSRO[WATCHDOG_EN] field description . .22
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .22
4.5 Recommended operating conditions . . . . . . . . . . . . . .23
4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . .26
4.6.1 Package thermal characteristics . . . . . . . . . . . .26
4.6.2 Power considerations . . . . . . . . . . . . . . . . . . . .26
4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .27
4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.7.2 I/O input DC characteristics . . . . . . . . . . . . . . . .27
4.7.3 I/O output DC characteristics. . . . . . . . . . . . . . .28
4.7.4 Output pin transition times . . . . . . . . . . . . . . . . .31
4.7.5 I/O pad current specification . . . . . . . . . . . . . . .31
4.8 RESET electrical characteristics. . . . . . . . . . . . . . . . . .35
4.9 Power management electrical characteristics. . . . . . . .37
4.9.1 Voltage regulator electrical characteristics . . . .37
4.9.2 Low voltage detector electrical characteristics .40
4.10 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.11 Flash memory electrical characteristics. . . . . . . . . . . . 42
4.11.1 Program/Erase characteristics . . . . . . . . . . . . . 42
4.11.2 Flash power supply DC characteristics . . . . . . 44
4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 45
4.12 Electromagnetic compatibility (EMC) characteristics. . 45
4.12.1 Designing hardened software to avoid
noise problems . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.12.2 Electromagnetic interference (EMI) . . . . . . . . . 46
4.12.3 Absolute maximum ratings (electrical sensitivity)46
4.13 Fast external crystal oscillator (4 to 16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 51
4.15 Fast internal RC oscillator (16 MHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.16 Slow internal RC oscillator (128 kHz) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 54
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.17.2 Input impedance and ADC accuracy . . . . . . . . 55
4.17.3 ADC electrical characteristics . . . . . . . . . . . . . 60
4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . 62
4.18.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . 63
4.18.3 JTAG characteristics . . . . . . . . . . . . . . . . . . . . 70
5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 70
5.1.1 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1.2 64 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
MPC5602D Microcontroller Data Sheet, Rev. 6
2 Freescale Semiconductor



Freescale Semiconductor MPC5602D
1 Introduction
Introduction
1.1 Document overview
This document describes the device features and highlights the important electrical and physical characteristics.
1.2 Description
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the
development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control
and seat control applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture
technology and designed specifically for embedded applications.
The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power
Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit), providing
improved code density. It operates at speeds of up to 48 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with the user’s implementations.
The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access
memory (SRAM) and internal flash memory.
Table 1. MPC5602D device comparison
Feature
CPU
Execution speed
Code flash memory
Data flash memory
SRAM
eDMA
ADC (12-bit)
CTU
Total timer I/O1
eMIOS
• Type X2
• Type Y3
• Type G4
• Type H5
SCI (LINFlex)
SPI (DSPI)
CAN (FlexCAN)
GPIO6
Device
MPC5601DxLH
MPC5601DxLL
MPC5602DxLH
MPC5602DxLL
e200z0h
Static – up to 48 MHz
128 KB
256 KB
64 KB (4 × 16 KB)
12 KB
16 KB
16 ch
16 ch
33 ch
16 ch
33 ch
16 ch
14 ch, 16-bit
28 ch, 16-bit
14 ch, 16-bit
28 ch, 16-bit
2 ch 5 ch 2 ch 5 ch
— 9 ch — 9 ch
7 ch 7 ch 7 ch 7 ch
4 ch 7 ch 4 ch 7 ch
3
2
1
45 79 45 79
Freescale Semiconductor
MPC5602D Microcontroller Data Sheet, Rev. 6
3







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