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PROTECTION PRODUCTS - EMIClampTM
Description
The EClampTM2384K is a low pass filter array with integrated TVS diodes. It is designed to suppress unwanted EMI/RFI signals and provide electrostatic discharge (ESD) protection in portable electronic equipment. This state-of-the-art device utilizes solid-state silicon-avalanche technology for superior clamping performance and DC electrical characteristics. It has been optimized for protection of color LCD panels in cellular phones and other portable electronics.
The device consists of four identical circuits comprised of TVS diodes for ESD protection, and a resistor capacitor network for EMI/RFI filtering. A series resistor value of 200Ω and a capacitance value of 12pF are used to achieve 30dB minimum attenuation from 800MHz to 2.7GHz. The TVS diodes provide effective suppression of ESD voltages in excess of ±15kV (air discharge) and ±8kV (contact discharge) per IEC 610004-2, level 4.
The EClamp2384K is in a 8-pin, RoHS/WEEE compliant, SLP1713P8 package. It measures 1.7 x 1.3 x 0.50mm. The leads are spaced at a pitch of 0.4mm and are finished with lead-free NiPdAu. The small package makes it ideal for use in portable electronics such as cell phones, digital still cameras, and PDAs.
Features
EClamp2384K
ESD/EMI Protection for Color LCD Interfaces
PRELIMINARY
Bidirectional EMI/RFI filter with integrated TVS for ESD protection
ESD protection to IEC 61000-4-2 (ESD) Level 4, ±15kV (air), ±8kV (contact)
Filter performance: 30dB minimum attenuation 800MHz to 2.7GHz
TVS working voltage: 5V Resistor: 200Ω +/− 15% Typical Capacitance: 12pF (VR = 2.5V) Protection and filtering for four lines Solid-state technology
Mechanical Characteristics
SLP1713P8 8-pin package RoHS/WEEE Compliant Nominal Dimensions: 1.7 x 1.3 x 0.50 mm Lead Pitch: 0.40mm Lead finish: NiPdAu Marking: Marking Code Packaging: Tape and Reel per EIA 481
Applications
Color LCD Protection Cell Phone CCD Camera Lines Clamshell Cell Phones
Circuit Diagram (Each Line)
Package Configuration
200 Ω IN
OUT
12pF 12pF
GND
1.70 12
1.30
0.40 BSC
0.50
Device Schematic (4X)
Revision 11/15/2007
8 Pin SLP package (Bottom Side View) Nominal Dimensions in mm
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PROTECTION PRODUCTS Maximum Ratings
Rating ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) Junction Temperature Operating Temperature Storage Temperature
Electrical Characteristics (T = 25oC)
Symbol
VESD TJ Top TSTG
EClamp2384K
PRELIMINARY
Value
+/- 17 +/- 12
125
-40 to +85
-55 to +150
Units
kV
oC oC oC
Parameter TVS Reverse Stand-Off Voltage TVS Reverse Breakdown Voltage TVS Reverse Leakage Current Total Series Resistance Capacitance
Symbol VRWM VBR IR R C1, C2
Total Capacitance
Cin
Conditions
It = 1mA VRWM = 3.0V Each Line
Each Line VR = 2.5V, f = 1MHz
Input to Gnd, Each Line
VR = 2.5V, f = 1MHz
Minimum Typical
68
170 200 10 12 20 24
Maximum 5 10 0.5
230 15
Units V V μA
Ohms pF
30 pF
© 2007 Semtech Corp.
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PROTECTION PRODUCTS Typical Characteristics
Typical Insertion Loss S21 (Each Line)
CH1 S21 LOG 6 dB / REF 0 dB
0 dB -6 dB -12 dB -18 dB
1
1: -12.305 dB 106.6 MHz
2: -35.996 dB 800 MHz
3: -38.349 dB 1.8 GHz
4: -36.250 dB 2.7 GHz
-24 dB
-30 dB
-36 dB -42 dB
24 3
-48 dB
1 MHz
START. 030 MHz
10 MHz
100 MHz
13 GHz GHz
STOP 3000.000000 MHz
ESD Clamping (+8kV Contact)
EClamp2384K
PRELIMINARY
Analog Crosstalk (Each Line)
CH1 S21 LOG 20 dB /REF 0 dB
START. 030 MHz
STOP 3000.000000 MHz
ESD Clamping (-8kV Contact)
Note: Data is taken with a 10x attenuator
Normalized Capacitance vs. Reverse Voltage (Normalized to 2.5 volts)
2
Note: Data is taken with a 10x attenuator
1.5
CJ(VR) / CJ(VR=2.5)
1
0.5
0 0 0.5 1 1.5 2 2.5 3 3.5
Reverse Voltage - VR (V)
© 2007 Semtech Corp.
f = 1 MHz 4 4.5 5
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EClamp2384K
PROTECTION PRODUCTS
Device Connection
The EClamp2384K is comprised of four identical circuits each consisting of a low pass filter for EMI/RFI suppression and dual TVS diodes for ESD protection. The device is in a 8-pin SLP package. Electrical connection is made to the 8 pins located at the bottom of the device. A center tab serves as the ground connection. The device has a flow through design for easy layout. Pin connections are noted in Figure 1. All path lengths should be kept as short as possible to minimize the effects of parasitic inductance in the board traces. Recommendations for the ground connection are given below.
PRELIMINARY
Figure 1 - Pin Identification and Configuration (Top Side View)
In 1 1
8 Out 1
In 2 Out 2 Gnd
In 3 Out 3
In 4 4
5 Out 4
Ground Connection Recommendation
Parasitic inductance present in the board layout will affect the filtering performance of the device. As frequency increases, the effect of the inductance becomes more dominant. This effect is given by Equation 1.
Pin 1-4 5-8 Center Tab
Identification Input Lines Output Lines
Ground
Equation 1: The Impedance of an Inductor at Freq.