2 Memory. IS49NLC93200 Datasheet

IS49NLC93200 Memory. Datasheet pdf. Equivalent

IS49NLC93200 Datasheet
Recommendation IS49NLC93200 Datasheet
Part IS49NLC93200
Description Common I/O RLDRAM 2 Memory
Feature IS49NLC93200; IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb (x9, x18, x36) Common I/O RLDRAM® 2 Memory FEATURES A.
Manufacture Integrated Silicon Solution
Datasheet
Download IS49NLC93200 Datasheet




Integrated Silicon Solution IS49NLC93200
IS49NLC93200,IS49NLC18160,IS49NLC36800
288Mb (x9, x18, x36) Common I/O RLDRAM® 2 Memory
FEATURES
ADVANCED INFORMATION
JUNE 2012
533MHz DDR operation (1.067 Gb/s/pin data
rate)
38.4Gb/s peak bandwidth (x36 at 533 MHz
clock frequency)
Reduced cycle time (15ns at 533MHz)
32ms refresh (8K refresh for each bank; 64K
refresh command must be issued in total each
32ms)
8 internal banks
Non-multiplexed addresses (address
multiplexing option available)
SRAM-type interface
Programmable READ latency (RL), row cycle
time, and burst sequence length
Balanced READ and WRITE latencies in order to
optimize data bus utilization
Data mask signals (DM) to mask signal of
WRITE data; DM is sampled on both edges of
DK.
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25-60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C; TA = 0°C to +70°C),
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
OPTIONS
Package:
144-ball FBGA (leaded)
144-ball FBGA (lead-free)
Configuration:
32Mx9
16Mx18
8Mx36
Clock Cycle Timing:
Speed Grade
-18
tRC 15
tCK 1.875
-25E
15
2.5
-25 -33 -5
20 20 20
2.5 3.3
5
Unit
ns
ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM® is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 06/20/2012
1



Integrated Silicon Solution IS49NLC93200
IS49NLC93200,IS49NLC18160,IS49NLC36800
1 Package Ballout and Description
1.1 288Mb (32Mx9) Common I/O BGA Ball-out (Top View)
1
A VREF
B VDD
C VTT
D A221
E A212
F A5
G A8
H BA2
J NF3
K DK
L REF#
M WE#
N A18
P A15
R VSS
T VTT
U VDD
V VREF
2
VSS
DNU4
DNU4
DNU4
DNU4
DNU4
A6
A9
NF3
DK#
CS#
A16
DNU4
DNU4
DNU4
DNU4
DNU4
ZQ
3
VEXT
DNU4
DNU4
DNU4
DNU4
DNU4
A7
VSS
VDD
VDD
VSS
A17
DNU4
DNU4
DNU4
DNU4
DNU4
VEXT
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5678
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ4
DQ5
DQ6
DQ7
DQ8
VEXT
11
TMS
DNU4
DNU4
QK0
DNU4
DNU4
A1
A4
BA0
BA1
A14
A11
DNU4
DNU4
DNU4
DNU4
DNU4
TDO
12
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
DQ*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
DNU,NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
I/O
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
9
2
2
2
1
3
1
1
31
4
144
NNoOteTs:ES:
1o12co..)pRnRtReneisesoeeecnrstrveevaederlddlvayfenfooddbrrfehfufuaotctsuruorprenfaeurunuatsesseueict.r.itTceeThcdhiuhsiasstsroeisgai.gncGtnTaealNhrliissiiDstsininc.mtsoetoranfcyoaalnnlynaedcdtereds.s
2in)puRtessigenravl.ed for future use. This signal is
i3n. Nteorfnunacltliyonc.oTnhnisescigtneadl isainndterhnaalslypcaonrnaesciteicd and has
cpahraarsiatictcehrairsatcitcesrisotifcsaonf aadcldocrkeisnspuint spiguntasl.iTghnisaml.ay
T3co4pco.pao)hnDrtnNainioosnsenointcemaiotccfletluatycduehnybtsdaoeecro.taaGcpTiconNohttnenDdiinsro..iesshnNcTitgtaaiocenhtslsdaelioylpsttfiohsabsaaGiirnetIgaN/tinOcefsDroaiO..ntTnlDiahcnilTlisysecisimcchnoetaannteyreandarobeplncctetottadeieo,dlGrnltyahiaNsnelltdsyDiechb.saes
opifnsaacreloHcikghi-nZ.put signal. This may optionally
be connected to GND.
4) Do not use. This signal is internally
connected and has parasitic characteristics
of a I/O. This may optionally be connected
to GND. Note that if ODT is enabled, these
pins will be connected to VTT.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 06/20/2012
2



Integrated Silicon Solution IS49NLC93200
IS49NLC93200,IS49NLC18160,IS49NLC36800
1.2 288Mb (16Mx18) Common I/O BGA Ball-out (Top View)
1
A VREF
B VDD
C VTT
D A221
E A212
F A5
G A8
H BA2
J NF3
K DK
L REF#
M WE#
N A18
P A15
R VSS
T VTT
U VDD
V VREF
2
VSS
DNU4
DNU4
DNU4
DNU4
DNU4
A6
A9
NF3
DK#
CS#
A16
DNU4
DNU4
QK1
DNU4
DNU4
ZQ
3
VEXT
DQ4
DQ5
DQ6
DQ7
DQ8
A7
VSS
VDD
VDD
VSS
A17
DQ14
DQ15
QK1#
DQ16
DQ17
VEXT
4
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
5678
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ9
DQ10
DQ11
DQ12
DQ13
VEXT
11
TMS
DNU4
DNU4
QK0
DNU4
DNU4
A1
A4
BA0
BA1
A14
A11
DNU4
DNU4
DNU4
DNU4
DNU4
TDO
12
TCK
VDD
VTT
VSS
A202
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
DQ*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
DNU,NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
I/O
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
18
2
4
2
1
3
1
1
20
4
144
NNoOteTs:ES:
1o1c2o..)pnRRtRneeiessoeeecnstrreevvadeerlddlvtyoeffoodbGrrNefffuuDoctt.ruuorrnfeeunuutessueecr..tTTeehhduiissstmsoeig.aGnyTaoNlhpisiDtsiion.mnteaarlnlyyablley
2co)nRneecsteedrvaendd hfaosrpfauratsuitricecuhasrea.ctTehrisitsicssiogfnaanlaidsdress
innptuetrsniganlalyl. connected and has parasitic
c3.hNaorfaucntcetiroins.tTichsisosifgnaanl ias dindterrensasllyincopnuntecstiegdnaanld. has
Tpahraissitmic achyaroapctteiroisntaiclsloyf baecloccokninnpeucttseidgntaol. TGhiNs mDa.y
3co4p.pao)DrtnNaioonsnointeaioccfltlutycuehnbsdaeecr.taacTiconohtnendinsr.iesshcTitgtaicenhssdaiolpstfiosasaGiirnIgaN/tnOesDrai..ntTliahcillisyscimchnoaantyrenaroepncctttaeieodlrnlyaiasnlltdyichbsaes
ocofnaneccltoecdktoiGnNpDu.tNsoitgentahal.t Tif OhDisTmis aenyabolpedti,othneaslely
bpienscaorne nHeigcht-eZd. to GND.
4) Do not use. This signal is internally
connected and has parasitic characteristics
of a I/O. This may optionally be connected
to GND. Note that if ODT is enabled, these
pins will be connected to VTT.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 06/20/2012
3







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