2 Memory. IS49NLS93200 Datasheet

IS49NLS93200 Memory. Datasheet pdf. Equivalent

IS49NLS93200 Datasheet
Recommendation IS49NLS93200 Datasheet
Part IS49NLS93200
Description Separate I/O RLDRAM 2 Memory
Feature IS49NLS93200; IS49NLS93200,IS49NLS18160 288Mb (x9, x18) Separate I/O RLDRAM® 2 Memory FEATURES ADVANCED INFORMAT.
Manufacture Integrated Silicon Solution
Datasheet
Download IS49NLS93200 Datasheet




Integrated Silicon Solution IS49NLS93200
IS49NLS93200,IS49NLS18160
288Mb (x9, x18) Separate I/O RLDRAM® 2 Memory
FEATURES
ADVANCED INFORMATION
SEPTEMBER 2012
533MHz DDR operation (1.067 Gb/s/pin data
rate)
38.4 Gb/s peak bandwidth (x18 Separate I/O at
533 MHz clock frequency)
Reduced cycle time (15ns at 533MHz)
32ms refresh (8K refresh for each bank; 64K
refresh command must be issued in total each
32ms)
8 internal banks
Non-multiplexed addresses (address
multiplexing option available)
SRAM-type interface
Programmable READ latency (RL), row cycle
time, and burst sequence length
Balanced READ and WRITE latencies in order to
optimize data bus utilization
Data mask signals (DM) to mask signal of
WRITE data; DM is sampled on both edges of
DK.
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25-60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C; TA = 0°C to +70°C),
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
OPTIONS
Package:
144-ball FBGA (leaded)
144-ball FBGA (lead-free)
Configuration:
32Mx9
16Mx18
Clock Cycle Timing:
Speed Grade
-18
-25E -25 -33 Unit
tRC 15
15
tCK 1.875 2.5
20 20 ns
2.5 3.3 ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM® is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 09/25/2012
1



Integrated Silicon Solution IS49NLS93200
IS49NLS93200,IS49NLS18160
1 Package Ballout and Description
1.1 288Mb (32Mx9) Separate I/O BGA Ball-out (Top View)
123
4 5678 9
10 11 12
A VREF
B VDD
VSS
DNU3
VEXT
DNU3
VSS
VSSQ
VSS VEXT TMS
TCK
VSSQ
Q0
D0 VDD
C
VTT
DNU3
DNU3
VDDQ
VDDQ
Q1
D1
VTT
D A221
DNU3
DNU3
VSSQ
VSSQ
QK0#
QK0
VSS
E A211
DNU3
DNU3
VDDQ
VDDQ
Q2
D2
A20
F A5
DNU3
DNU3
VSSQ
VSSQ
Q3
D3 QVLD
G A8 A6 A7 VDD
VDD
A2
A1
A0
H BA2 A9 VSS VSS
J NF2 NF2 VDD VDD
VSS
VDD
VSS
VDD
A4
BA0
A3
CK
K DK
DK# VDD VDD
VDD
VDD
BA1
CK#
L REF#
CS#
VSS
VSS
VSS VSS A14 A13
M WE#
A16
A17
VDD
VDD A12 A11 A10
N A18
DNU3
DNU3
VSSQ
VSSQ
Q4
D4
A19
P
A15
DNU3
DNU3
VDDQ
VDDQ
Q5
D5
DM
R VSS DNU3 DNU3 VSSQ
T
VTT
DNU3
DNU3
VDDQ
VSSQ
Q6
D6
VSS
VDDQ
Q7
D7
VTT
U VDD
DNU3
DNU3
VSSQ
VSSQ
Q8
D8 VDD
V VREF ZQ VEXT VSS
VSS VEXT TDO
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
D*
Q*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
DNU,NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
Input data
Output data
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
9
9
2
2
2
1
3
1
1
22
4
144
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connected and has parasitic
characteristics of a clock input signal.
This may optionally be connected to
GND.
4) Do not use. This signal is internally
connected and has parasitic
characteristics of a I/O. This may
optionally be connected to GND. Note
that if ODT is enabled, these pins will be
connected to VTT.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 09/25/2012
2



Integrated Silicon Solution IS49NLS93200
IS49NLS93200,IS49NLS18160
1.2 288Mb (16Mx18) Separate I/O BGA Ball-out (Top View)
12
3
4 5678 9
10 11 12
A VREF VSS VEXT VSS
VSS
VEXT
TMS
TCK
B VDD
D4
Q4 VSSQ
VSSQ
Q0
D0 VDD
C VTT
D A221
D5
D6
Q5 VDDQ
Q6 VSSQ
VDDQ
VSSQ
Q1
QK0#
D1
QK0
VTT
VSS
E A212
D7
Q7 VDDQ
VDDQ
Q2
D2 A202
F A5 D8 Q8 VSSQ
VSSQ
Q3
D3 QVLD
G A8 A6 A7 VDD
VDD A2 A1 A0
H BA2 A9 VSS VSS
J NF3 NF3 VDD VDD
VSS VSS
A4
VDD VDD BA0
A3
CK
K DK
DK# VDD VDD
VDD VDD BA1
CK#
L REF#
CS#
VSS
VSS
VSS VSS A14 A13
M WE#
A16
A17
VDD
VDD A12 A11 A10
N A18 D14 Q14 VSSQ
VSSQ
Q9
D9 A19
P A15 D15 Q15 VDDQ
VDDQ
Q10
D10
DM
R VSS
QK1 QK1# VSSQ
VSSQ
Q11
D11
VSS
T VTT D16 Q16 VDDQ
VDDQ
Q12
D12
VTT
U VDD D17 Q17 VSSQ
VSSQ
Q13
D13
VDD
V VREF ZQ VEXT VSS
VSS
VEXT
TDO
TDI
Symbol
VDD
VSS
VDDQ
VSSQ
VEXT
VREF
VTT
A*
BA*
D*
Q*
DK*
QK*
CK*
DM
CS#,WE#,REF#
ZQ
QVLD
NF
T*
Total
Description
Supply voltage
Ground
DQ power supply
DQ Ground
Supply voltage
Reference voltage
Termination voltage
Address - A0-22
Banks - BA0-2
Input data
Output data
Input data clock(Differential inputs)
Output data clocks(outputs)
Input clocks (CK, CK#)
Input data mask
Command control pins
External impedance (25–60Ω)
Data valid
Do not use, No function
JTAG - TCK,TMS,TDO,TDI
Ball count
16
16
8
12
4
2
4
23
3
18
18
2
4
2
1
3
1
1
2
4
144
NNoOteTs:ES:
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connected and has parasitic characteristics of
a clock input signal. This may optionally be
connected to GND.
4) Do not use. This signal is internally
connected and has parasitic characteristics of
a I/O. This may optionally be connected to
GND. Note that if ODT is enabled, these pins
will be connected to VTT.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 09/25/2012
3







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