2 Memory. IS49NLS96400A Datasheet

IS49NLS96400A Memory. Datasheet pdf. Equivalent

IS49NLS96400A Datasheet
Recommendation IS49NLS96400A Datasheet
Part IS49NLS96400A
Description Separate I/O RLDRAM 2 Memory
Feature IS49NLS96400A; IS49NLS96400A, IS49NLS18320A 576Mb (64Mbx9, 32Mbx18) Seperate I/O RLDRAM 2 Memory ADVANCED INFORMA.
Manufacture Integrated Silicon Solution
Datasheet
Download IS49NLS96400A Datasheet




Integrated Silicon Solution IS49NLS96400A
IS49NLS96400A, IS49NLS18320A
576Mb (64Mbx9, 32Mbx18)
Seperate I/O RLDRAM2 Memory
ADVANCED INFORMATION
SEPTEMBER 2014
FEATURES
533MHz DDR operation (1.067 Gb/s/pin data rate)
38.4Gb/s peak bandwidth (x18 at 533 MHz clock
frequency)
Reduced cycle time (15ns at 533MHz)
32ms refresh (16K refresh for each bank; 128K
refresh command must be issued in total each
32ms)
8 internal banks
Non-multiplexed addresses (address
multiplexing option available)
SRAM-type interface
Programmable READ latency (RL), row cycle
time, and burst sequence length
Balanced READ and WRITE latencies in order
to optimize data bus utilization
Data mask signals (DM) to mask signal of
WRITE data; DM is sampled on both edges of
DK.
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data
and output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
25-60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
IEEE 1149.1 compliant JTAG boundary scan
Operating temperature:
Commercial
(TC = 0° to +95°C)
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
OPTIONS
Package:
144-ball FBGA (leaded)
144-ball FBGA (lead-free)
Configuration:
64Mx9
32Mx18
Clock Cycle Timing:
Speed Grade
-18
-25E -25 -33 Unit
tRC 15 15 20 20 ns
tCK 1.875 2.5 2.5 3.3 ns
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at
any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for
products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAMis a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc. www.issi.com
Rev. 00A, 9/10/2014
1



Integrated Silicon Solution IS49NLS96400A
IS49NLS96400A, IS49NLS18320A
1 Package Ballout and Description
1.1 576Mb (64Mx9) Separate I/O BGA Ball-out (Top View)
1 2 3 4 5678
A
VREF
VSS
VEXT
VSS
B
VDD
DNU3
DNU3
VSSQ
C
VTT
DNU3
DNU3
VDDQ
D
A221
DNU3 DNU3
VSSQ
E
A21
DNU3
DNU3
VDDQ
F
A5
DNU3
DNU3
VSSQ
G A8 A6 A7 VDD
H
BA2 A9
VSS
VSS
J
NF2
NF2
VDD
VDD
K DK DK# VDD VDD
L REF# CS# VSS VSS
M
WE#
A16
A17
VDD
N
A18
DNU3
DNU3
VSSQ
P
A15
DNU3
DNU3
VDDQ
R
VSS
DNU3
DNU3
VSSQ
T
VTT
DNU3
DNU3
VDDQ
U
VDD
DNU3
DNU3
VSSQ
V
VREF
ZQ
VEXT
VSS
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
Q0
Q1
QK0#
Q2
Q3
A2
VSS
VDD
VDD
VSS
A12
Q4
Q5
Q6
Q7
Q8
VEXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D4
D5
D6
D7
D8
TD0
12
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Notes:
1. Reserved for future use. This may optionally be connected to GND.
2. No Function. This signal is internally connected and has parasitic characteristics of a
clock input signal. This may optionally be connected to GND.
3. Do not use. This signal is internally connected and has parasitic characteristics of a
I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins are High-Z.
Integrated Silicon Solution, Inc. www.issi.com
Rev. 00A, 9/10/2014
2



Integrated Silicon Solution IS49NLS96400A
IS49NLS96400A, IS49NLS18320A
1.2 576Mb (32Mx18) Separate I/O BGA Ball-out (Top View)
1 2 3 4 5678
A
VREF
VSS
VEXT
VSS
B VDD D4 Q4 VSSQ
C VTT D5 Q5 VDDQ
D
A221
D6
Q6 VSSQ
E
A212
D7
Q7 VDDQ
F A5 D8 Q8 VSSQ
G A8 A6 A7 VDD
H
BA2 A9
VSS
VSS
J
NF3
NF3
VDD
VDD
K DK DK# VDD VDD
L REF# CS# VSS VSS
M
WE#
A16
A17
VDD
N
A18
D14
Q14
VSSQ
P
A15
D15
Q15
VDDQ
R
VSS
QK1
QK1# VSSQ
T
VTT
D16
Q16
VDDQ
U
VDD
D17
Q17
VSSQ
V
VREF
ZQ
VEXT
VSS
9
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
10
VEXT
Q0
Q1
QK0#
Q2
Q3
A2
VSS
VDD
VDD
VSS
A12
Q9
Q10
Q11
Q12
Q13
VEXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D9
D10
D11
D12
D13
TD0
12
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
Notes: 1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an
address input signal. This may optionally be connected to GND.
3. No Function. This signal is internally connected and has parasitic characteristics of a
clock input signal. This may optionally be connected to GND.
Integrated Silicon Solution, Inc. www.issi.com
Rev. 00A, 9/10/2014
3







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