Microphone ADC. CS53L30 Datasheet

CS53L30 ADC. Datasheet pdf. Equivalent

CS53L30 Datasheet
Recommendation CS53L30 Datasheet
Part CS53L30
Description Low-Power Quad-Channel Microphone ADC
Feature CS53L30; CS53L30 Low-Power Quad-Channel Microphone ADC with TDM Output Analog Input and ADC Features Syste.
Manufacture Cirrus Logic
Datasheet
Download CS53L30 Datasheet




Cirrus Logic CS53L30
CS53L30
Low-Power Quad-Channel Microphone ADC with TDM Output
Analog Input and ADC Features
System Features
91-dB dynamic range (A-weighted) @ 0-dB gain
–84-dB THD+N @ 0-dB gain
Four fully differential inputs: Four analog mic/line inputs
Four analog programmable gain amplifiers
–6 to +12 dB, in 0.5-dB steps
+10 or +20 dB boost for mic input
Four mic bias generators
MUTE pin for quick mic mute and programmable quick
power down
Digital Processing Features
Volume control, mute, programmable high-pass filter,
noise gate
Two digital mic (DMIC) interfaces
Digital Output Features
Two DMIC SCLK generators
Four-channel I2S output or TDM output. Four CS53L30s
can be used to output 16 channels of 24-bit 16-kHz
sample rate data on a single TDM line.
Native (no PLL required) support for 6-/12-MHz, 6.144-/
12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master
clock rates and 8- to 48-kHz audio sample rates
Master or Slave Mode. Clock dividers can be used to
generate common audio clocks from single-master clock
input.
Low power consumption
Less than 4.5-mW stereo (16 kHz) analog mic record
Less than 2.5-mW mono (8 kHz) analog mic record
Selectable mic bias and digital interface logic voltages
High-speed (400-kHz) I²C control port
Available in 30-ball WLCSP and 32-pin QFN
Applications
Voice-recognition systems
Advanced headsets and telephony systems
Voice recorders
Digital cameras and video cameras
IN1+/DMIC1_SD
IN1–
IN2+
IN2–
IN3+/DMIC2_SD
IN3–
IN4+
IN4–
MIC 1_BIAS
MIC 2_BIAS
MIC 3_BIAS
MIC 4_BIAS
VA
LDO VD
+
+
+10 or +20 dB
+ ADC1A
+ ADC1B
–6 to +12 dB,
0.5 dB steps MCLK_INT
CS53L30
Digital Processing
HPF, Noise
Gate, Volume,
Mute
2
+
+
+10 or +20 dB
+
ADC2A
+
ADC2B
–6 to +12 dB,
0.5 dB steps MCLK_INT
MIC1 Bias
MIC2 Bias
MIC3 Bias
MIC4 Bias
DMIC
HPF, Noise
Gate, Volume,
Mute
2
Control Port
M C LK_I N T
Clock Divider
Synchronizer
Level Shifters
4
Synchronous
SRC
Audio
Serial Port
RESET
DMIC1_SCLK
Control
SYNC MCLK
Serial Port
VP
DMIC2_SCLK
Port
MUTE
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2013–2019
(All Rights Reserved)
DS992F3
DEC'19



Cirrus Logic CS53L30
CS53L30
General Description
The CS53L30 is a high-performance, low-power, quad-channel ADC. It is designed for use in multiple-mic applications
while consuming minimal board space and power.
The flexible ADC inputs can accommodate four channels of analog mic or line-input data in differential, pseudodifferential,
or single-ended mode, or four channels of digital mic data. The analog input path includes a +10- to +20-dB boost and a
–6- to +12-dB PGA. Digital mic data bypasses the analog gain circuits and is fed directly to the decimators.
Four mic bias generators are integrated into the device. The device also includes two digital mic serial clock outputs.
The CS53L30 includes several digital signal processing features such as high-pass filters, noise gate, and volume control.
The device can output its four channels of audio data over two I2S ports or a single TDM port. Additionally, up to four
CS53L30s can be used to output up to 16 channels of data over a single TDM line. This is done by setting the appropriate
frame slots for each device, and each device then alternates between outputting data and setting the output pin to high
impedance.
The CS53L30 can operate as a serial port clock master or slave. In Master Mode, clock dividers are used to generate the
internal master clock and audio clocks from either the 6-/12-MHz, 6.144-/12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz
master clock.
The device is powered from VA, a 1.8-V nominal supply and VP, a typical battery supply. An internal LDO on the VA supply
powers the device’s digital core. The VP supply powers the mic bias generators and the AFE.
The CS53L30 is controlled by an I2C control port. A reset pin is also included. The device is available in a 30-ball 0.4-mm
pitch WLCSP package and 32-pin 5 x 5-mm QFN package.
2 DS992F3



Cirrus Logic CS53L30
CS53L30
Table of Contents
1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Characteristics and Specifications . . . . . . . . . . . . . . . . . . . . . . 9
Table 3-1. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 9
Table 3-2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3-3. Combined ADC On-Chip Analog, Digital Filter, SRC, and
DMIC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3-4. ADC High-Pass Filter (HPF) Characteristics . . . . . . . . . . . . . 9
Table 3-5. Analog-Input-to-Serial-Port Characteristics . . . . . . . . . . . . . 10
Table 3-6. MIC BIAS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3-7. Power-Supply Rejection Ratio (PSRR) Characteristics . . . . 11
Table 3-8. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3-9. Switching Specifications—Digital Mic Interface . . . . . . . . . . 14
Table 3-10. Specifications—I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3-11. Switching Specifications—Time-Division Multiplexed
(TDM) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3-12. Switching Specifications—I2C Control Port . . . . . . . . . . . . 16
Table 3-13. Digital Interface Specifications and Characteristics . . . . . . 17
Table 3-14. Thermal Overload Detection Characteristics . . . . . . . . . . . 17
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 Capture-Path Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Digital Microphone (DMIC) Interface . . . . . . . . . . . . . . . . . . 23
4.6 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 TDM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.8 Synchronous Sample-Rate Converter (SRC) . . . . . . . . . . . . 33
4.9 Multichip Synchronization Protocol . . . . . . . . . . . . . . . . . . . 34
4.10 Input Path Source Selection and Powering . . . . . . . . . . . . 34
4.11 Thermal Overload Notification . . . . . . . . . . . . . . . . . . . . . . 34
4.12 MUTE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.13 Power-Up and Power-Down Control . . . . . . . . . . . . . . . . . 35
4.14 I2C Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.15 QFN Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Systems Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1 Octal Microphone Array to the Audio Serial Port . . . . . . . . . 38
5.2 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.4 Capture-Path Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.5 MCLK Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.6 Frequency Response Considerations . . . . . . . . . . . . . . . . . 44
5.7 Connecting Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6 Register Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.1 Device ID A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.2 Device ID C and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.3 Device ID E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.4 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.5 Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.6 MCLK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.7 Internal Sample Rate Control . . . . . . . . . . . . . . . . . . . . . . . . 48
7.8 Mic Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.9 ASP Configuration Control . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.10 ASP Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.11 ASP TDM TX Control 1–4 . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.12 ASP TDM TX Enable 1–6 . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.13 ASP Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.14 Soft Ramp Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.15 LRCK Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.16 LRCK Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.17 MUTE Pin Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.18 MUTE Pin Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.19 Input Bias Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.20 Input Bias Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.21 DMIC1 Stereo Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.22 DMIC2 Stereo Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.23 ADC1/DMIC1 Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.24 ADC1/DMIC1 Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.25 ADC1 Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.26 ADC1 Noise Gate Control . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.27 ADC1A/1B AFE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.28 ADC1A/1B Digital Volume . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.29 ADC2/DMIC2 Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.30 ADC2/DMIC2 Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.31 ADC2 Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.32 ADC2 Noise Gate Control . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.33 ADC2A/2B AFE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.34 ADC2A/2B Digital Volume . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.35 Device Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.36 Device Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8 Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9 Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.1 Digital Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2 PGA Gain Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.3 Dynamic Range Versus Sampling Frequency . . . . . . . . . . . 63
9.4 FFTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1 WLCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.2 QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DS992F3
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