CLOCK CONVERTER. LS7084N Datasheet

LS7084N CONVERTER. Datasheet pdf. Equivalent

LS7084N Datasheet
Recommendation LS7084N Datasheet
Part LS7084N
Description QUADRATURE CLOCK CONVERTER
Feature LS7084N; LSI/CSI LS7083N LS7084N U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747.
Manufacture LSI
Datasheet
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LSI LS7084N
LSI/CSI
LS7083N
LS7084N
U® L
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800
QUADRATURE CLOCK CONVERTER
June 2015
FEATURES:
• x1 and x4 mode selection
• Up to 16MHz output clock frequency
• Programmable output clock pulse width
• On-chip filtering of inputs for optical or
magnetic encoder applications.
• TTL and CMOS compatible I/Os
• +3V to +12V operation (VDD - VSS)
LS7083N, LS7084N (DIP);
LS7083NS, LS7084NS (SOIC) - See Figure 1
Applications:
• Interface incremental encoders to Up / Down Counters
(See Figure 6A and Figure 6B)
• Interface rotary encoders to Digital Potentiometers
(See Figure 7)
DESCRIPTION:
The LS7083N and LS7084N are CMOS quadrature clock con-
verters. Quadrature clocks derived from optical or magnetic en-
coders, when applied to the A and B inputs of the LS7083N or
LS7084N, are converted to strings of Up Clocks and Down
Clocks ( LS7083N) or to a Clock and an Up/Down direction con-
trol (LS7084N). These outputs can be interfaced directly with
standard Up/Down counters for direction and position sensing of
the encoder.
INPUT/OUTPUT DESCRIPTION:
RBIAS (Pin 1)
Input for external component connection. A resistor connected
between this input and VSS adjusts the output clock pulse width
(Tow). For proper operation, the output clock pulse width must be
less than or equal to the A, B pulse separation (TOW TPS).
VDD (Pin 2)
Supply Voltage positive terminal.
VSS (Pin 3)
Supply Voltage negative terminal.
A (Pin 4)
Quadrature Clock Input A. This input has a filter circuit to validate
input logic level and eliminate encoder dither.
B (Pin 5)
Quadrature Clock Input B. This input has a filter circuit identical
to input A.
Mode (Pin 6)
Mode is a 3-state input to select resolutions x1, x2 or x4. The se-
lected resolution multiplies the input quadrature clock rate by 1, 2
and 4, respectively, in producing the outputs UPCK / DNCK and
CLK (see Figure 2).
The Mode input logic levels selects resolutions as follows:
Logic 0 = x1 Float = x2 Logic 1 = x4
PIN ASSIGNMENT - TOP VIEW
RBIAS 1
VDD (+V ) 2
VSS (-V ) 3
A4
8 UPCK
7 DNCK
6 MODE
5B
RBIAS 1
VDD (+V ) 2
VSS (-V ) 3
A4
8 CLK
7 UP/DN
6 MODE
5B
FIGURE 1
LS7083N - DNCK (Pin 7)
In LS7083N, this is the DOWN Clock Output. This output consists of
low-going pulses generated when A input lags the B input.
LS7084N - UP/DN (Pin 7)
In LS7084N, this is the count direction indication output. When A
input leads the B input, the UP/DN output goes high indicating that
the count direction is UP. When A input lags the B input, UP/DN
output goes low, indicating that the count direction is DOWN.
LS7083N - UPCK (Pin 8)
In LS7083N, this is the UP Clock output. This output consists of
low-going pulses generated when A input leads the B input.
LS7084N - CLK (Pin 8)
In LS7084N, this is the combined UP Clock and DOWN Clock out-
put. The count direction at any instant is indicated by the UP/DN
output (Pin 7).
NOTE: For the LS7084N, the timing of CLK and UP/DN requires
that the counter interfacing with LS7084N counts on the rising edge
of the CLK pulses.
7083N/84N-062315 -1



LSI LS7084N
ABSOLUTE MAXIMUM RATINGS:
PARAMETER
SYMBOL
VALUE
UNITS
DC Supply Voltage
Voltage at any input
Operating temperature
Storage temperature
VDD - VSS
VIN
TA
TSTG
DC ELECTRICAL CHARACTERISTICS:
PARAMETER
SYMBOL
16 V
VSS-0.3 to VDD+0.3
V
-20 to +85
ºC
-55 to 150
ºC
(Unless otherwise specified VDD = 3V to 12V and TA = -20ºC to +85ºC)
MIN TYP MAX UNITS
CONDITION
Supply Voltage
Supply Current
MODE INPUT:
VDD 3 - 12 V
-
IDD - 1.5 1.65 mA VDD = 12V, all input frequencies=0 Hz and RBIAS = 2MΩ
Logic 0
Logic 1
Logic Float
Logic 0 Input Current
Logic 1 Input Current
A,B INPUTS:
Vml - - 0.5 V
Vmh
VDD - 0.5
-
-
V
Vmf (VDD/2) - 0.5 VDD/2 (VDD/2) + 0.5 V
Iml - 2.2 4.2 μA
Iml - 3.5 6.9 μA
Iml - 8.3 16.2 μA
Imh - -2 -9.8 μA
Imh - -3.4 -6.6 μA
Imh - -8.2 -16 μA
-
-
VDD = 3V
VDD = 5V
VDD = 12V
VDD = 3V
VDD = 5V
VDD = 12V
Logic 0
Logic 1
Input Current
RBIAS INPUT:
VABl - - 0.25VDD V
VABh 0.7VDD - - V
IABlk - 0 10 nA
-
-
-
External Resistor
ALL OUTPUTS:
RB 2K - 10M Ω
-
Sink Current
Source Current
Iol - -3.2 - mA
Iol - -4.8 - mA
Iol - -7.2 - mA
Ioh - 1.7 - mA
Ioh - 2.2 - mA
Ioh - 3.1 - mA
TRANSIENT CHARACTERISTICS (TA = -20ºC to +85ºC)
PARAMETER
SYMBOL
MIN
TYP
MAX UNITS
CONDITION
Output Clock Pulse Width
A,B INPUTS:
TOW
TOW
TOW
540
180
60
ns VDD = 3V
ns VDD = 5V
ns VDD = 12V
Validation Delay
Phase Delay
Pulse Width
Frequency
Input to output Delay
TVD - 450 -
TVD - 200 -
TVD - 90 -
TPS TVD+TOW
s
TPW
2TPS
-
s
fA,B -
1/(2TPW)
Hz
TDS
-
490 565
ns
VDD = 3V
VDD = 5V
VDD = 12V
-
-
-
VDD = 3V
TDS
-
220 345
ns
VDD = 5V
TDS
7083N/7084N0623152
-
125 135
ns
VDD = 12V



LSI LS7084N
 
7083N/84N0623153  
 
The information included herein is believed to be
accurate and reliable. However LSI Computer
Systems, Inc assumes no responsibilities to
inaccuracies, or to any infringements of patent rights
of others which may result from its use.
 







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