QUADRATURE COUNTER. LS7267 Datasheet
U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
24-BIT DUAL-AXIS QUADRATURE COUNTER
• Up to 50MHz count frequency in non-quadrature mode;
Up to 5.6MHz clock frequency (22 x 106 counts/sec) in
x4 quadrature mode.
• Dual 24-bit counters to support X and Y axes in
motion control applications. • Dual 24-bit comparators.
• Digital filtering of the input quadrature clocks
• Programmable 8-bit separate filter clock prescalers
for each axis.
• Error flags for noise exceeding filter band width.
• Programmable Index Input and other programmable I/Os.
• Independent mode programmability for each axis.
• Programmable count modes:
Quadrature (x1, x2, x4) / Non-quadrature,
Normal / Modulo-N / Range Limit / Non-Recycle,
Binary / BCD.
• 8-bit 3-State data I/O bus.
• 3V to 5.5V operation (VDD - VSS).
• TTL/CMOS compatible I/Os.
• LS7267 (DIP); LS7267-S (SOIC); LS7267-TS (TSSOP)
V DD (+5V) 3
V SS (GND ) 12
LS7267 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X,
whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode
of the three most significant bits (D7 - D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects
between control and data information for Read/Write. Following is a complete list of LS7267 registers.
Preset Registers: XPR and YPR
Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data
7 07 07 0
Counters: XCNTR and YCNTR
Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its
associated A/B inputs. Each CNTR can be loaded with the content of its associated PR.
Output Latches: XOL and YOL
Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded
into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read
7 07 0 7 0
Byte Pointers: XBP and YBP
The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is
addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is
automatically incremented to address the next byte.
Flag Register: XFLAG and YFLAG
The FLAG registers hold the status information of the CNTRs and can be read on the data bus. All bits excepting
the E and the IDX bits change dynamically to represent the instantaneous status of the CNTR's. In contrast the E
and the IDX bits are latched. Once set they can only be reset via the RLD registers.
7 6 5 4 32 1 0
BT: Borrow Toggle flip-flop.
Toggles every time CNTR underflows.
CT: Carry toggle flip-flop.
Toggles every time CNTR overflows.
CPT: Compare toggle flip-flop.
Toggles every time PR equals CNTR.
S: Sign flag. Set to 1 when CNTR underflows.
Reset to 0 when CNTR overflows.
E: Error latch. Set to 1 when parameter t4 or t5 is violated (see p.8 for t4 and t5)
Irrelevant in non-quadrature mode.
U/D: Up/Down flag. Set to 1 when counting up
and reset to 0 when counting down.
IDX: Index. Set to 1 when designated index input transitions to active level.
0: Not used. Always reset to 0.
Filter Clock Prescalers: XPSC and YPSC
Each PSC is an 8-bit programmable modulo-n down counter, driven by the FCK input. The division factor n is stored
into each PSC from its associated PR register low byte, PR0. The PSCs provide the ability to generate independent
filter clock frequencies for each channel used for filtering the quadrature clocks applied at the A and B inputs in
quadrature mode.The same filter clocks are also used for filtering the designated INDEX inputs.
The effective internal filter clock frequency is: fFCKn = ( fFCK/(n+1) ) , where n = PSC = 0 to h'FF and fFCK is the clock
frequency at the FCK input. For proper operation the required condition is: fFCKn > 8fQA (or 8fQB), where fQA (or fQB)
is the frequency at A (or B) input. The FCK pin is not used in non-quadrature mode and should be tied off to VDD.
Reset and Load Signal Decoders: XRLD and YRLD
Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer
CNTR to OL, reset CNTR, reset FLAG and reset BP.
7 6 5 4 3 21 0
1: Reset BP
0 : NOP
: Reset CNTR
: Reset BT, CT, CPT,S, IDX
: Reset E
1 : Transfer PR to CNTR
0 (Note: All 24-bits are transferred in parallel)
0 : Transfer CNTR to OL
1 (Note: All 24-bits are transferred in parallel)
1 : Transfer PR0 to PSC
: Select RLD
0 : Select the RLD addressed by X/Y input
1 : Select both XRLD and YRLD together
(Note: D7 = 1 overrides X/Y input)
Counter Mode Registers: XCMR and YCMR
The CNTR operational mode is programmed by writing into the CMRs.
7 6543 210
0 : Binary count
1 : BCD count
0 : Normal count
1 : Range Limit
: Non-recycle count
1 : Modulo-N
0 : Non-quadrature
: Quadrature X1
0 : Quadrature X2
1 : Quadrature X4
1 : Select CMR
0: Select CMR addressed by X/Y input
1: Select both XCMR and YCMR together (Note: D7=1 overrides X/Y input)
DEFINITIONS OF COUNT MODES:
Range Limit. In range limit count mode, an upper and a lower limit is set, mimicking limit switches in the me-
chanical counterpart. The upper limit is set by the content of the PR and the lower limit is set to be 0. The
CNTR freezes at CNTR = PR when counting up and at CNTR = 0 when counting down. At either of these limits,
the counting is resumed only when the count direction is reversed.
Non-Recycle. In non-recycle count mode, the CNTR is disabled, whenever a count overflow or underflow takes
place. The end of cycle is marked by the generation of a Carry (in Up Count) or a Borrow (in Down Count). The
CNTR is re-enabled when a reset or load operation is performed on the CNTR.
Modulo-N. In modulo-N count mode, a count boundary is set between 0 and the content of PR. When counting
up, at CNTR = PR, the CNTR is reset to 0 and the up count is continued from that point. When counting down,
at CNTR = 0, the CNTR is loaded with the content of PR and down count is continued from that point.
The modulo-N is true bidirectional in that the divide-by-N output frequency is generated in both up and down di-
rection of counting for same N and does not require the complement of N in the UP instance. In frequency di-
vider application, the modulo-N output frequency can be obtained at either the Compare (FLG1) or the Borrow
(FLG2) output. Modulo-N output frequency, fN = (fi / (N+ 1) ) where fi = Input count frequency and N = PR.
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.