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LS7267 Dataheets PDF



Part Number LS7267
Manufacturers LSI
Logo LSI
Description 24-BIT DUAL-AXIS QUADRATURE COUNTER
Datasheet LS7267 DatasheetLS7267 Datasheet (PDF)

LSI/CSI LS7267 U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 24-BIT DUAL-AXIS QUADRATURE COUNTER OCT 2015 FEATURES: • Up to 50MHz count frequency in non-quadrature mode; Up to 5.6MHz clock frequency (22 x 106 counts/sec) in x4 quadrature mode. • Dual 24-bit counters to support X and Y axes in motion control applications. • Dual 24-bit comparators. • Digital filtering of the input quadrature clocks • Programmable 8-bit sep.

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LSI/CSI LS7267 U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 24-BIT DUAL-AXIS QUADRATURE COUNTER OCT 2015 FEATURES: • Up to 50MHz count frequency in non-quadrature mode; Up to 5.6MHz clock frequency (22 x 106 counts/sec) in x4 quadrature mode. • Dual 24-bit counters to support X and Y axes in motion control applications. • Dual 24-bit comparators. • Digital filtering of the input quadrature clocks • Programmable 8-bit separate filter clock prescalers for each axis. • Error flags for noise exceeding filter band width. • Programmable Index Input and other programmable I/Os. • Independent mode programmability for each axis. • Programmable count modes: Quadrature (x1, x2, x4) / Non-quadrature, Normal / Modulo-N / Range Limit / Non-Recycle, Binary / BCD. • 8-bit 3-State data I/O bus. • 3V to 5.5V operation (VDD - VSS). • TTL/CMOS compatible I/Os. • LS7267 (DIP); LS7267-S (SOIC); LS7267-TS (TSSOP) PIN ASSIGNMENT TOP VIEW LS7267 LSI YLCNTR/YLOL 1 FCK 2 V DD (+5V) 3 D0 4 D1 5 D2 6 D3 7 D4 8 D5 9 D6 10 D7 11 V SS (GND ) 12 C/D 13 WR 14 28 YRCNTR/YABG 27 YFLG1 26 YFLG2 25 YA 24 YB 23 XFLG2 22 XFLG1 21 XB 20 XA 19 XLCNTR/XLOL 18 XRCNTR/XABG 17 X/Y 16 RD 15 CS LS7267 Registers: LS7267 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X, whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode of the three most significant bits (D7 - D5) of the data-bus. CS input enables the IC for Read/Write. C/D input selects between control and data information for Read/Write. Following is a complete list of LS7267 registers. Preset Registers: XPR and YPR Each of these PRs are 24-bit wide. 24-bit data can be written into a PR, one byte at a time, in a sequence of three data write cycles. PR 7 07 07 0 HI BYTE (PR2) MID BYTE (PR1) LO BYTE (PR0) Counters: XCNTR and YCNTR Each of these CNTRs are 24-bit synchronous Up/Down counters. The count clocks for each CNTR is derived from its associated A/B inputs. Each CNTR can be loaded with the content of its associated PR. Output Latches: XOL and YOL Each OL is 24-bits wide. In effect, the OLs are the output ports for the CNTRs. Data from each CNTR can be loaded into its associated OL and then read back on the data-bus, one byte at a time, in a sequence of three data Read cycles. OL 7 07 0 7 0 HI BYTE (OL2) MID BYTE (OL1) LO BYTE (OL0) Byte Pointers: XBP and YBP The Read and Write operations on an OL or a PR always accesses one byte at a time. The byte that is accessed is addressed by one of the BPs. At the end of every data Read or Write cycle on an OL or a PR, the associated BP is automatically incremented to address the next byte. 7267-102215-1 Flag Register: XFLAG and YFLAG The FLAG registers hold the status information of the CNTRs and can be read on the data bus. All bits excepting the E and the IDX bits change dynamically to represent the instantaneous status of the CNTR's. In contrast the E and the IDX bits are latched. Once set they can only be reset via the RLD registers. FLAG 7 6 5 4 32 1 0 BT: Borrow Toggle flip-flop. Toggles every time CNTR underflows. CT: Carry toggle flip-flop. Toggles every time CNTR overflows. CPT: Compare toggle flip-flop. Toggles every time PR equals CNTR. S: Sign flag. Set to 1 when CNTR underflows. Reset to 0 when CNTR overflows. E: Error latch. Set to 1 when parameter t4 or t5 is violated (see p.8 for t4 and t5) Irrelevant in non-quadrature mode. U/D: Up/Down flag. Set to 1 when counting up and reset to 0 when counting down. IDX: Index. Set to 1 when designated index input transitions to active level. 0: Not used. Always reset to 0. Filter Clock Prescalers: XPSC and YPSC Each PSC is an 8-bit programmable modulo-n down counter, driven by the FCK input. The division factor n is stored into each PSC from its associated PR register low byte, PR0. The PSCs provide the ability to generate independent filter clock frequencies for each channel used for filtering the quadrature clocks applied at the A and B inputs in quadrature mode.The same filter clocks are also used for filtering the designated INDEX inputs. The effective internal filter clock frequency is: fFCKn = ( fFCK/(n+1) ) , where n = PSC = 0 to h'FF and fFCK is the clock frequency at the FCK input. For proper operation the required condition is: fFCKn > 8fQA (or 8fQB), where fQA (or fQB) is the frequency at A (or B) input. The FCK pin is not used in non-quadrature mode and should be tied off to VDD. Reset and Load Signal Decoders: XRLD and YRLD Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer CNTR to OL, reset CNTR, reset FLAG and reset BP. RLD 7 6 5 4 3 21 0 7267-091615-2 0: NOP 1: Reset BP 0 0 : NOP 1 0 : Reset CNTR 0 1 : Reset BT, CT, CPT,S, IDX 1 1 : Reset E 0 0 : NOP 1 : Transfer PR to CNTR 0 (Note: All 24-bits are tr.


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