D/A Converter. CS4385A Datasheet

CS4385A Converter. Datasheet pdf. Equivalent

CS4385A Datasheet
Recommendation CS4385A Datasheet
Part CS4385A
Description 192-kHz 8-Channel D/A Converter
Feature CS4385A; CS4385A 114-dB, 192-kHz 8-Channel D/A Converter Features Description  Advanced Multi-bit Delta .
Manufacture Cirrus Logic
Datasheet
Download CS4385A Datasheet




Cirrus Logic CS4385A
CS4385A
114-dB, 192-kHz 8-Channel D/A Converter
Features
Description
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Automatic Detection of Sample Rates up to
192 kHz
114 dB Dynamic Range
-100 dB THD+N
Direct Stream Digital® (DSD) Mode
– Non-decimating Volume Control
– On-chip 50 kHz Filter
– Matched PCM and DSD Analog Output Levels
Compatible with Industry-standard Time
Division Multiplexed (TDM) Serial Interface in
both Hardware and Software Modes
Selectable Digital Filters
Volume Control with 1/2 dB Step Size and Soft
Ramp
Low Clock-jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
The CS4385A is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
half-dB step size volume control, ATAPI channel mix-
ing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma mod-
ulator which includes mismatch-shaping technology
that eliminates distortion due to capacitor mismatch.
Following this stage is a multi-element switched capac-
itor stage and low-pass filter with differential analog
outputs.
The CS4385A also has a proprietary DSD processor
that allows for volume control and 50 kHz on-chip filter-
ing without an intermediate decimation stage. It also
offers an optional path for direct DSD conversion by di-
rectly using the multi-element, switched capacitor array.
The CS4385A is available in a 48-pin LQFP package in
both Commercial (-40°C to +85°C) and Automotive
(-40°C to +105°C) grades. Please see “Ordering Infor-
mation” on page 53 for complete details.
The CS4385A accepts PCM data at sample rates from
4 kHz to 216 kHz, Direct Stream Digital audio data, and
delivers excellent sound quality. These features are ide-
al for multi-channel audio systems, including SACD
players, A/V receivers, digital TV’s, mixing consoles, ef-
fects processors, sound cards, and automotive audio
systems.
Control Port Supply = 1.8 V to 5 V
Digital Supply = 2.5 V
Analog Supply = 5 V
Hardware Mode or
I2C/SPI Software Mode
Control Data
Reset
Serial Audio Port
Supply = 1.8 V to 5 V
PCM Serial
Audio Input
TDM Serial
Audio Input
DSD Audio
Input
Register/Hardware
Configuration
Internal Voltage
Reference
Volume
8 Controls
Digital
Filters
Multi-bit
Modulators
DSD Processor
-Volume control
-50 kHz filter
Switch-Cap
DAC and
Analog Filters
8
Eight Channels
of Differential
Outputs
8
External Mute
Control
2
Mute Signals
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2014
(All Rights Reserved)
APRIL '14
DS837F2



Cirrus Logic CS4385A
CS4385A
TABLE OF CONTENTS
1. PIN DESCRIPTION .............................................................................................................................. 6
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ..................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 8
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ............................................................. 9
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ............................................................ 10
POWER AND THERMAL CHARACTERISTICS .................................................................................. 11
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ...................................... 12
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED) .............. 13
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE ............................................. 13
DIGITAL CHARACTERISTICS ............................................................................................................. 14
SWITCHING CHARACTERISTICS - PCM ........................................................................................... 15
SWITCHING CHARACTERISTICS - DSD ........................................................................................... 16
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT .............................................. 17
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................................. 18
3. TYPICAL CONNECTION DIAGRAM .................................................................................................. 19
4. APPLICATIONS ................................................................................................................................... 21
4.1 Master Clock ................................................................................................................................... 21
4.2 Mode Select .................................................................................................................................... 22
4.3 Digital Interface Formats ................................................................................................................ 23
4.3.1 OLM #1 .................................................................................................................................. 24
4.3.2 OLM #2 .................................................................................................................................. 24
4.3.3 OLM #3 .................................................................................................................................. 24
4.3.4 OLM #4 .................................................................................................................................. 25
4.3.5 TDM ....................................................................................................................................... 25
4.4 Oversampling Modes ...................................................................................................................... 25
4.5 Interpolation Filter ........................................................................................................................... 26
4.6 De-Emphasis .................................................................................................................................. 26
4.7 ATAPI Specification ........................................................................................................................ 27
4.8 Direct Stream Digital (DSD) Mode .................................................................................................. 27
4.9 Grounding and Power Supply Arrangements ................................................................................. 28
4.9.1 Capacitor Placement ............................................................................................................. 28
4.10 Analog Output and Filtering .......................................................................................................... 29
4.11 The MUTEC Outputs .................................................................................................................... 30
4.12 Recommended Power-Up Sequence ........................................................................................... 30
4.12.1 Hardware Mode ................................................................................................................... 30
4.12.2 Software Mode .................................................................................................................... 31
4.13 Recommended Procedure for Switching Operational Modes ....................................................... 31
5. CONTROL PORT INTERFACE ............................................................................................................ 32
5.1 MAP Auto Increment ...................................................................................................................... 32
5.2 I²C Mode ......................................................................................................................................... 32
5.2.1 I²C Write ................................................................................................................................ 32
5.2.2 I²C Read ................................................................................................................................ 32
5.3 SPI Mode ........................................................................................................................................ 33
5.3.1 SPI Write ............................................................................................................................... 33
5.4 Memory Address Pointer (MAP) .................................................................................................... 34
5.4.1 INCR (Auto Map Increment Enable) ...................................................................................... 34
5.4.2 MAP4-0 (Memory Address Pointer) ...................................................................................... 34
6. REGISTER QUICK REFERENCE ....................................................................................................... 35
7. REGISTER DESCRIPTION .................................................................................................................. 37
7.1 Chip I.D. and Revision (Address 01h) ............................................................................................ 37
7.1.1 Chip I.D. [Read Only] ............................................................................................................ 37
2 DS837F2



Cirrus Logic CS4385A
CS4385A
7.1.2 Chip Revision [Read Only] .................................................................................................... 37
7.2 Mode Control 1 (Address 02h) ....................................................................................................... 37
7.2.1 Control Port Enable (CPEN) .................................................................................................. 37
7.2.2 Freeze Controls (FREEZE) ................................................................................................... 37
7.2.3 PCM/DSD Selection (DSD/PCM) .......................................................................................... 38
7.2.4 DAC Pair Disable (DACx_DIS) .............................................................................................. 38
7.2.5 Power Down (PDN) ............................................................................................................... 38
7.3 PCM Control (Address 03h) ........................................................................................................... 38
7.3.1 Digital Interface Format (DIF) ................................................................................................ 38
7.3.2 Functional Mode (FM) ........................................................................................................... 39
7.4 DSD Control (Address 04h) ............................................................................................................ 39
7.4.1 DSD Mode Digital Interface Format (DSD_DIF) .................................................................... 39
7.4.2 Direct DSD Conversion (DIR_DSD) ...................................................................................... 40
7.4.3 Static DSD Detect (STATIC_DSD) ........................................................................................ 40
7.4.4 Invalid DSD Detect (INVALID_DSD) ..................................................................................... 40
7.4.5 DSD Phase Modulation Mode Select (DSD_PM_MODE) ..................................................... 40
7.4.6 DSD Phase Modulation Mode Enable (DSD_PM_EN) ......................................................... 40
7.5 Filter Control (Address 05h) ........................................................................................................... 41
7.5.1 Interpolation Filter Select (FILT_SEL) ................................................................................... 41
7.6 Invert Control (Address 06h) .......................................................................................................... 41
7.6.1 Invert Signal Polarity (Inv_xx) ................................................................................................ 41
7.7 Group Control (Address 07h) ......................................................................................................... 41
7.7.1 Mutec Pin Control (MUTEC) .................................................................................................. 41
7.7.2 Channel A Volume = Channel B Volume (Px_A=B) .............................................................. 42
7.7.3 Single Volume Control (SNGLVOL) ...................................................................................... 42
7.8 Ramp and Mute (Address 08h) ...................................................................................................... 42
7.8.1 Soft Ramp and Zero Cross Control (SZC) ............................................................................ 42
7.8.2 Soft Volume Ramp-Up After Error (RMP_UP) ...................................................................... 43
7.8.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) .................................................... 43
7.8.4 PCM Auto-Mute (PAMUTE) .................................................................................................. 43
7.8.5 DSD Auto-Mute (DAMUTE) ................................................................................................... 43
7.8.6 Mute Polarity and Detect (MUTEP1:0) .................................................................................. 44
7.9 Mute Control (Address 09h) ........................................................................................................... 44
7.9.1 Mute (MUTE_xx) ................................................................................................................... 44
7.10 Mixing Control (Address 0Ah, 0Dh, 10h, 13h) .............................................................................. 45
7.10.1 De-Emphasis Control (PX_DEM1:0) ................................................................................... 45
7.10.2 ATAPI Channel Mixing and Muting (ATAPI) ........................................................................ 46
7.11 Volume Control (Address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h) ............................................ 47
7.11.1 Digital Volume Control (xx_VOL7:0) ................................................................................... 47
7.12 PCM Clock Mode (Address 16h) .................................................................................................. 47
7.12.1 Master Clock Divide by 2 Enable (MCLKDIV) ..................................................................... 47
8. FILTER PLOTS ..................................................................................................................................... 48
9. PARAMETER DEFINITIONS ................................................................................................................ 52
10. PACKAGE DIMENSIONS ................................................................................................................. 53
11. ORDERING INFORMATION .............................................................................................................. 53
12. REFERENCES .................................................................................................................................... 54
13. REVISION HISTORY ......................................................................................................................... 55
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