Ethernet PHY. 82579 Datasheet

82579 PHY. Datasheet pdf. Equivalent

82579 Datasheet
Recommendation 82579 Datasheet
Part 82579
Description Gigabit Ethernet PHY
Feature 82579; Intel® 82579 Gigabit Ethernet PHY Datasheet v2.1 Product Features  General  Security & Manageab.
Manufacture Intel
Datasheet
Download 82579 Datasheet





Intel 82579
Intel® 82579 Gigabit Ethernet PHY
Datasheet v2.1
Product Features
General
Security & Manageability
— 10 BASE-T IEEE 802.3 specification
— Intel® vPro support with appropriate Intel
conformance
chipset componnets (82579LM SKU)
— 100 BASE-TX IEEE 802.3 specification
— MACSec support1
conformance
Performance
— 1000 BASE-T IEEE 802.3 specification
— Jumbo Frames (up to 9 kB)2
conformance
— 802.1Q & 802.1p
— Energy Efficient Ethernet (EEE) IEEE
— Receive Side Scaling (RSS)
802.3az support [Low Power Idle (LPI)
mode]
— Two Queues (Tx & Rx)
— IEEE 802.3u auto-negotiation conformance Power
— Supports carrier extension (half duplex)
— Flexible power configuration: use either the
— Loopback modes for diagnostics
— Advanced digital baseline wander correction
PCH 1.05 Vdc or iSVR.
— Reduced power consumption during normal
operation and power down modes
— Automatic MDI/MDIX crossover at all
speeds of operation
— Integrated Intel® Auto Connect Battery
Saver (ACBS)
— Automatic polarity correction
— Single-pin LAN Disable for easier BIOS
— MDC/MDIO management interface
implementation
— Flexible filters in PHY to reduce integrated
LAN controller power
— Fully integrated Switching Voltage
Regulator (iSVR)
— Smart speed operation for automatic speed
— Low Power LinkUp (LPLU)
reduction on faulty cable plants
MAC/PHY Interconnect
— PMA loopback capable (no echo cancel)
— PCIe-based interface for active state
— 802.1as/1588 conformance
operation (S0 state)
— Intel® Stable Image Platform Program
(SIPP)
— SMBus-based interface for host and
management traffic (Sx low power state)
— iSCSI Boot
— Network proxy/ARP Offload support
Package/Design
— 48-pin package, 6 x 6 mm with a 0.4 mm
lead pitch and an Exposed Pad* for ground
— Three configurable LED outputs
— Integrated MDI interface termination
resistors to reduce BOM costs
— Reduced BOM cost by sharing SPI flash with
PCH
1. MACSec is not compatible with Intel® Active Management Technology
2. Jumbo Frames are not compatible with MACSec.
Reference Number: 324990-007



Intel 82579
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The 82579 GbE PHY may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
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Intel 82579
Datasheet — Intel® 82579 Gigabit Ethernet PHY
Contents
1.0 Introduction .............................................................................................................. 1
1.1 Scope ................................................................................................................ 1
1.2 Overview ........................................................................................................... 1
1.3 Main Flows ......................................................................................................... 2
1.4 References ......................................................................................................... 3
1.5 Product SKUs, Codes, and Device IDs .................................................................... 3
1.6 Supported Operating Systems............................................................................... 4
2.0 Interconnects ............................................................................................................ 7
2.1 Introduction ....................................................................................................... 7
2.2 PCIe-Based ........................................................................................................ 7
2.3 SMBus ............................................................................................................... 8
2.4 Transitions between SMBus and PCIe interfaces ...................................................... 9
2.5 Intel® 6 Series Express Chipset/82579 – SMBus/PCIe Interconnects ........................ 10
3.0 Pin Interface ........................................................................................................... 13
3.1 Pin Assignment ................................................................................................. 13
4.0 Package................................................................................................................... 17
4.1 Package Type and Mechanical ............................................................................. 17
4.2 Package Electrical and Thermal Characteristics ...................................................... 18
4.3 Power and Ground Requirements......................................................................... 18
4.4 Ball Mapping..................................................................................................... 19
5.0 Initialization............................................................................................................ 23
5.1 Power Up ......................................................................................................... 23
5.2 Reset Operation ................................................................................................ 24
5.3 Timing Parameters ............................................................................................ 25
6.0 Power Management and Delivery............................................................................. 27
6.1 Power Delivery.................................................................................................. 28
6.2 Power Management ........................................................................................... 28
7.0 Device Functionality ................................................................................................ 35
7.1 Tx Flow ............................................................................................................ 35
7.2 Rx Flow............................................................................................................ 35
7.3 Flow Control ..................................................................................................... 36
7.4 Wake Up .......................................................................................................... 38
7.5 Network Proxy Functionality................................................................................ 46
7.6 Loopback ......................................................................................................... 52
8.0 Electrical and Timing Specifications......................................................................... 53
8.1 Introduction ..................................................................................................... 53
8.2 Operating Conditions ......................................................................................... 53
8.3 Power Delivery.................................................................................................. 54
8.4 I/O DC Parameter ............................................................................................. 56
8.5 Discrete/Integrated Magnetics Specifications......................................................... 60
8.6 Mechanical ...................................................................................................... 60
8.7 Oscillator/Crystal Specifications........................................................................... 60
9.0 Programmer’s Visible State ..................................................................................... 63
9.1 Terminology ..................................................................................................... 63
9.2 MDIO Access .................................................................................................... 64
9.3 Addressing ....................................................................................................... 64
9.4 Address Map..................................................................................................... 65
9.5 PHY Registers (Page 0) ...................................................................................... 67
9.6 Port Control Registers (Page 769)........................................................................ 88
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