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AUDIO CODEC. VS1003 Datasheet

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AUDIO CODEC. VS1003 Datasheet






VS1003 CODEC. Datasheet pdf. Equivalent




VS1003 CODEC. Datasheet pdf. Equivalent





Part

VS1003

Description

MP3/WMA AUDIO CODEC



Feature


VS1003 VS1003 - MP3/WMA AUDIO CODEC Fe atures • Decodes MPEG 1 & 2 audio lay er III (CBR +VBR +ABR); WMA 4.0/4.1/7/8 /9 all profiles (5-384kbit/s); WAV (PC M + IMA ADPCM); General MIDI / SP-MIDI files • Encodes IMA ADPCM from micro phone or line input • Streaming suppo rt for MP3 and WAV • Bass and treble controls • Operates with a single 12. .13 MHz clock • Internal PLL clo.
Manufacture

VLSI

Datasheet
Download VS1003 Datasheet


VLSI VS1003

VS1003; ck multiplier • Low-power operation High-quality on-chip stereo DAC with no phase error between channels • Ste reo earphone driver capable of driv- in g a 30Ω load • Separate operating v oltages for analog, digital and I/O • 5.5 KiB On-chip RAM for user code / da ta • Serial control and data interfac es • Can be used as a slave co-proces sor • SPI flash boot for special ap.


VLSI VS1003

plications • UART for debugging purpos es • New functions may be added with soft- ware and 4 GPIO pins Description VS1003 is a single-chip MP3/WMA/MIDI a udio decoder and ADPCM encoder. It cont ains a high-performance, proprietary lo w-power DSP processor core VS_DSP4, wor king data memory, 5 KiB instruction RAM and 0.5 KiB data RAM for user applicat ions, serial control a.


VLSI VS1003

nd input data interfaces, 4 general purp ose I/O pins, an UART, as well as a hig h-quality variablesample-rate mono ADC and stereo DAC, followed by an earphone amplifier and a common buffer. VS1003 receives its input bitstream through a serial input bus, which it listens to as a system slave. The input stream is decoded and passed through a digital vo lume control to an 1.

Part

VS1003

Description

MP3/WMA AUDIO CODEC



Feature


VS1003 VS1003 - MP3/WMA AUDIO CODEC Fe atures • Decodes MPEG 1 & 2 audio lay er III (CBR +VBR +ABR); WMA 4.0/4.1/7/8 /9 all profiles (5-384kbit/s); WAV (PC M + IMA ADPCM); General MIDI / SP-MIDI files • Encodes IMA ADPCM from micro phone or line input • Streaming suppo rt for MP3 and WAV • Bass and treble controls • Operates with a single 12. .13 MHz clock • Internal PLL clo.
Manufacture

VLSI

Datasheet
Download VS1003 Datasheet




 VS1003
VS1003
VS1003 - MP3/WMA AUDIO CODEC
Features
Decodes MPEG 1 & 2 audio layer III
(CBR +VBR +ABR); WMA 4.0/4.1/7/8/9
all profiles (5-384kbit/s); WAV (PCM +
IMA ADPCM); General MIDI / SP-MIDI
files
Encodes IMA ADPCM from microphone
or line input
Streaming support for MP3 and WAV
Bass and treble controls
Operates with a single 12..13 MHz clock
Internal PLL clock multiplier
Low-power operation
High-quality on-chip stereo DAC with no
phase error between channels
Stereo earphone driver capable of driv-
ing a 30load
Separate operating voltages for analog,
digital and I/O
5.5 KiB On-chip RAM for user code /
data
Serial control and data interfaces
Can be used as a slave co-processor
SPI flash boot for special applications
UART for debugging purposes
New functions may be added with soft-
ware and 4 GPIO pins
Description
VS1003 is a single-chip MP3/WMA/MIDI au-
dio decoder and ADPCM encoder. It contains
a high-performance, proprietary low-power DSP
processor core VS_DSP4, working data mem-
ory, 5 KiB instruction RAM and 0.5 KiB data
RAM for user applications, serial control and
input data interfaces, 4 general purpose I/O
pins, an UART, as well as a high-quality variable-
sample-rate mono ADC and stereo DAC, fol-
lowed by an earphone amplifier and a com-
mon buffer.
VS1003 receives its input bitstream through
a serial input bus, which it listens to as a
system slave. The input stream is decoded
and passed through a digital volume control
to an 18-bit oversampling, multi-bit, sigma-
delta DAC. The decoding is controlled via a
serial control bus. In addition to the basic de-
coding, it is possible to add application spe-
cific features, like DSP effects, to the user
RAM memory.
mic
audio
line
audio
GPIO
VS1003
MIC AMP
MUX
4
GPIO
DREQ
SO
SI
SCLK
XCS
XDCS
Serial
Data/
Control
Interface
RX
TX UART
Mono
ADC
Stereo
DAC
VSDSP4
Clock
multiplier
Instruction
RAM
Instruction
ROM
Stereo Ear−
phone Driver
X ROM
audio
L
R
output
X RAM
Y ROM
Y RAM
Version: 1.08, 2014-12-19
1




 VS1003
VS1003
CONTENTS
Contents
VS1003
1
Table of Contents
2
List of Figures
5
1 Licenses
6
2 Disclaimer
6
3 Definitions
6
4 Characteristics & Specifications
7
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 7
4.3 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.5 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.6 Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . 9
4.7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.7.1 Line input ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.7.2 Microphone input ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.7.3 RIGHT and LEFT outputs . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Packages and Pin Descriptions
12
5.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.2 BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 LQFP-48 and BGA-49 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 13
6 Connection Diagram, LQFP-48
15
7 SPI Buses
16
7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2.1 VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . 16
7.2.2 VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4 Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . 17
7.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4.2 SDI in VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . 17
7.4.3 SDI in VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . 18
7.4.4 Passive SDI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.5 Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . 18
7.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.5.2 SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5.3 SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.6 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.7 SPI Examples with SM_SDINEW and SM_SDISHARED set . . . . . . . . . . . 21
7.7.1 Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Version: 1.08, 2014-12-19
2




 VS1003
VS1003
CONTENTS
7.7.2 Two SDI Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.7.3 SCI Operation in Middle of Two SDI Bytes . . . . . . . . . . . . . . . 22
8 Functional Description
23
8.1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2 Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2.1 Supported MP3 (MPEG layer III) Formats . . . . . . . . . . . . . . . 23
8.2.2 Supported WMA Formats . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2.3 Supported RIFF WAV Formats . . . . . . . . . . . . . . . . . . . . . . 25
8.2.4 Supported MIDI Formats . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.3 Data Flow of VS1003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.4 Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.5 Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.6 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.6.1 SCI_MODE (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.6.2 SCI_STATUS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.6.3 SCI_BASS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.6.4 SCI_CLOCKF (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.6.5 SCI_DECODE_TIME (RW) . . . . . . . . . . . . . . . . . . . . . . . 33
8.6.6 SCI_AUDATA (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.6.7 SCI_WRAM (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.6.8 SCI_WRAMADDR (W) . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.6.9 SCI_HDAT0 and SCI_HDAT1 (R) . . . . . . . . . . . . . . . . . . . . 34
8.6.10 SCI_AIADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.6.11 SCI_VOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.6.12 SCI_AICTRL[x] (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 Operation
37
9.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4 ADPCM Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4.1 Activating ADPCM mode . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4.2 Reading IMA ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . 38
9.4.3 Adding a RIFF Header . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.4.4 Playing ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.5 Sample Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . 40
9.4.6 Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.5 SPI Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.6 Play/Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.7 Feeding PCM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.8 SDI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.8.1 Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.8.2 Pin Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.8.3 Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.8.4 SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10 VS1003 Registers
10.1 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 VS1003 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
45
45
Version: 1.08, 2014-12-19
3



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