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VS1003 Dataheets PDF



Part Number VS1003
Manufacturers VLSI
Logo VLSI
Description MP3/WMA AUDIO CODEC
Datasheet VS1003 DatasheetVS1003 Datasheet (PDF)

VS1003 VS1003 - MP3/WMA AUDIO CODEC Features • Decodes MPEG 1 & 2 audio layer III (CBR +VBR +ABR); WMA 4.0/4.1/7/8/9 all profiles (5-384kbit/s); WAV (PCM + IMA ADPCM); General MIDI / SP-MIDI files • Encodes IMA ADPCM from microphone or line input • Streaming support for MP3 and WAV • Bass and treble controls • Operates with a single 12..13 MHz clock • Internal PLL clock multiplier • Low-power operation • High-quality on-chip stereo DAC with no phase error between channels • Stereo earphone drive.

  VS1003   VS1003


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VS1003 VS1003 - MP3/WMA AUDIO CODEC Features • Decodes MPEG 1 & 2 audio layer III (CBR +VBR +ABR); WMA 4.0/4.1/7/8/9 all profiles (5-384kbit/s); WAV (PCM + IMA ADPCM); General MIDI / SP-MIDI files • Encodes IMA ADPCM from microphone or line input • Streaming support for MP3 and WAV • Bass and treble controls • Operates with a single 12..13 MHz clock • Internal PLL clock multiplier • Low-power operation • High-quality on-chip stereo DAC with no phase error between channels • Stereo earphone driver capable of driv- ing a 30Ω load • Separate operating voltages for analog, digital and I/O • 5.5 KiB On-chip RAM for user code / data • Serial control and data interfaces • Can be used as a slave co-processor • SPI flash boot for special applications • UART for debugging purposes • New functions may be added with soft- ware and 4 GPIO pins Description VS1003 is a single-chip MP3/WMA/MIDI audio decoder and ADPCM encoder. It contains a high-performance, proprietary low-power DSP processor core VS_DSP4, working data memory, 5 KiB instruction RAM and 0.5 KiB data RAM for user applications, serial control and input data interfaces, 4 general purpose I/O pins, an UART, as well as a high-quality variablesample-rate mono ADC and stereo DAC, followed by an earphone amplifier and a common buffer. VS1003 receives its input bitstream through a serial input bus, which it listens to as a system slave. The input stream is decoded and passed through a digital volume control to an 18-bit oversampling, multi-bit, sigmadelta DAC. The decoding is controlled via a serial control bus. In addition to the basic decoding, it is possible to add application specific features, like DSP effects, to the user RAM memory. mic audio line audio GPIO VS1003 MIC AMP MUX 4 GPIO DREQ SO SI SCLK XCS XDCS Serial Data/ Control Interface RX TX UART Mono ADC Stereo DAC VSDSP4 Clock multiplier Instruction RAM Instruction ROM Stereo Ear− phone Driver X ROM audio L R output X RAM Y ROM Y RAM Version: 1.08, 2014-12-19 1 VS1003 CONTENTS Contents VS1003 1 Table of Contents 2 List of Figures 5 1 Licenses 6 2 Disclaimer 6 3 Definitions 6 4 Characteristics & Specifications 7 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.6 Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . 9 4.7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.7.1 Line input ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.7.2 Microphone input ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.7.3 RIGHT and LEFT outputs . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Packages and Pin Descriptions 12 5.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.1 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.2 BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 LQFP-48 and BGA-49 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 13 6 Connection Diagram, LQFP-48 15 7 SPI Buses 16 7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2.1 VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . 16 7.2.2 VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . 16 7.3 Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4 Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . 17 7.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4.2 SDI in VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . 17 7.4.3 SDI in VS1001 Compatibility Mode . . . . . . . . . . . . . . . . . . . 18 7.4.4 Passive SDI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.5 Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . 18 7.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.5.2 SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5.3 SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.6 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.7 SPI Examples with SM_SDINEW and SM_SDISHARED set . . . . . . . . . . . 21 7.7.1 Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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