Document
74LVC1G14
Single Schmitt-trigger inverter
Rev. 13 — 15 March 2016
Product data sheet
1. General description
The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt-trigger action at the input makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V). 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Unlimited rise and fall times Input accepts voltages up to 5 V Multiple package options ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Specified from 40 C to +85 C and 40 C to +125 C.
3. Applications
Wave and pulse shaper Astable multivibrator Monostable multivibrator
NXP Semiconductors
74LVC1G14
Single Schmitt-trigger inverter
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC1G14GW 40 C to +125 C TSSOP5
74LVC1G14GV 74LVC1G14GM
40 C to +125 C 40 C to +125 C
SC-74A XSON6
74LVC1G14GF
40 C to +125 C XSON6
74LVC1G14GN 40 C to +125 C XSON6
74LVC1G14GS 40 C to +125 C XSON6
74LVC1G14GX 40 C to +125 C X2SON5
Description
Version
plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
plastic surface-mounted package; 5 leads
SOT753
plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 1.45 0.5 mm
plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads; 6 terminals; body 0.9 1.0 0.35 mm
SOT1115
extremely thin small outline package; no leads; 6 terminals; body 1.0 1.0 0.35 mm
SOT1202
X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 0.8 0.35 mm
SOT1226
5. Marking
Table 2. Marking Type number 74LVC1G14GW 74LVC1G14GV 74LVC1G14GM 74LVC1G14GF 74LVC1G14GN 74LVC1G14GS 74LVC1G14GX
Marking code[1] VF V14 VF VF VF VF VF
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
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PQD
Fig 1. Logic symbol
PQD
Fig 2. IEC logic symbol
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Fig 3. Logic diagram
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PQD
74LVC1G14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 15 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 21
NXP Semiconductors
7. Pinning information
7.1 Pinning
/9&*
QF $
9&&
*1'
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DDE
Fig 4. Pin configuration SOT353-1 and SOT753
74LVC1G14
Single Schmitt-trigger inverter
/9&*
QF
9&&
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QF
*1'
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DDE 7UDQVSDUHQWWRSYLHZ
Fig 5. Pin configuration SOT886
/9&*
QF $
9&& QF
*1'
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DDH
7UDQVSDUHQWWRSYLHZ
Fig 6. Pin configuration SOT891, SOT1115 and SOT1202
7.2 Pin description
Table 3. Symbol
n.c. A GND Y n.c. VCC
Pin description
Pin TSSOP5 and X2SON5 1 2 3 4 5
/9&*
QF
*1'
9&&
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DDD 7UDQVSDUHQWWRSYLHZ
Fig 7. Pin configuration SOT1226 (X2SON5)
XSON6 1 2 3 4 5 6
Description
not connected data input ground (0 V) data output not connected supply voltage
74LVC1G14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 13 — 15 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 21
NXP Semiconductors
74LVC1G14
Single Schmitt-trigger inverter
8. Functional description
Table 4. Input A L H
Function table[1]
[1] H = HIGH voltage level; L = LOW voltage level
9. Limiting values
Output Y H L
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage VI input voltage VO output voltage
Active mode Power-down mode
0.5
[1] 0.5
[1][2]
0.5
[1][2]
0.5
+6.5 +6.5 VCC + 0.5 +6.5
V V V V
IIK
input clamping current
VI < 0 V
IOK output clamping current VO > VCC or VO < 0 V
IO output current
VO = 0 V to VCC
50 - mA - 50 mA - 50 mA
ICC IGND Tstg Ptot
supply current ground current storage temperature total power dissipation
Tamb = 40 C to +125 C
100 65 [3] -
+100 -
+150 250
mA mA C mW
[1] The input and output v.