IS66WVE2M16BLL

IS66WVE2M16BLL 3.0V Core Async/Page PSRAM Overview The IS66WVE2M16BLL is an integrated memory device containing 32Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. Features  Asynchronous and page mode interface  Dual voltage rails for optional performance  VDD 2.7V~3.6V, VDDQ 2.7V~3.6V  Page mode read access  Interpage Read access : 70ns  Intrapage Read access : 20ns  Low Power Consumption  Asynchronous Operation < 30 mA  Intrapage Read < 18mA  Standby < 180 uA (max.)  Deep power-down (DPD) < 3uA (Typ)  Low Power Feature  Temperature Controlled Refresh  Partial Array Refresh  Deep power-down (DPD) mode  Operating temperature Range Industrial -40°C~85°C  Packages: 48-ball TFBGA, 48-pin TSOP-I Notes : 1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at [email protected] for additional information. Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information,...