IS66WVE4M16EALL/BLL/CLL IS67WVE4M16EALL/BLL/CLL
64Mb Async/Page PSRAM
PRELIMINARY INFORMATION Overview The IS66/67WVE4M1...
IS66WVE4M16EALL/BLL/CLL IS67WVE4M16EALL/BLL/CLL
64Mb Async/Page PSRAM
PRELIMINARY INFORMATION Overview The IS66/67WVE4M16EALL/BLL/CLL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Asynchronous and page mode interface Dual voltage rails for optional performance
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V Page mode read access Interpage Read access : 55ns, 70ns Intrapage Read access : 20ns Low Power Consumption Asynchronous Operation < 30 mA Intrapage Read < 23mA Standby < 200 uA (max.) Deep power-down (DPD)
ALL/CLL: < 3µA (Typ) BLL: < 10µA (Typ)
Low Power Feature Temperature Controlled Refresh Partial Array Refresh Deep power-down (DPD) mode
Operating temperature Range Industrial: -40°C~85°C Automotive A1: -40°C~85°C
Packages: 48-ball TFBGA
Notes: 1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM Marketing at
[email protected]
for additional information.
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