DatasheetsPDF.com

IS65WV12816BLL Dataheets PDF



Part Number IS65WV12816BLL
Manufacturers ISSI
Logo ISSI
Description ULTRA LOW POWER CMOS STATIC RAM
Datasheet IS65WV12816BLL DatasheetIS65WV12816BLL Datasheet (PDF)

IS65WV12816ALL IS65WV12816BLL ISSI® 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM PRELIMINARY INFORMATION JUNE 2006 FEATURES • High-speed access time: 55ns, 70ns • CMOS low power operation: 36 mW (typical) operating 9 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply: 1.65V to 2.2V VDD (65WV12816ALL) 2.5V to 3.6V VDD (65WV12816BLL) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • 2.

  IS65WV12816BLL   IS65WV12816BLL



Document
IS65WV12816ALL IS65WV12816BLL ISSI® 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM PRELIMINARY INFORMATION JUNE 2006 FEATURES • High-speed access time: 55ns, 70ns • CMOS low power operation: 36 mW (typical) operating 9 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply: 1.65V to 2.2V VDD (65WV12816ALL) 2.5V to 3.6V VDD (65WV12816BLL) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • 2CS Option Available • Temperature Offerings: Option A: 0 to 70oC Option A1: –40 to +85oC Option A2: –40 to +105oC Option A3: –40 to +125oC • Lead-free available DESCRIPTION The ISSI IS65WV12816ALL/ IS65WV12816BLL are high- speed, 2M bit static RAMs organized as 128K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS65WV12816ALL and IS65WV12816BLL are packged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CS2 CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00E 06/08/06 1 IS65WV12816ALL, IS65WV12816BLL ISSI® PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) (Package Code B) 1 23 45 6 48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2) 1 23 45 6 A LB OE A0 A1 A2 N/C B I/O8 UB A3 A4 CSI I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 44-Pin mini TSOP (Type II) (Package Code T) A4 A3.


IS65WV12816ALL IS65WV12816BLL IS62WV20488EALL


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)