IS65WV25616BLL

IS65WV25616ALL IS65WV25616BLL ISSI® 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM PRELIMINARY INFORMATION JUNE 2006 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby TTL compatible interface levels Single power supply 1.65V--2.2V VDD (65WV25616ALL) 2.5V--3.6V VDD (65WV25616BLL) Fully static operation: no clock or refresh required Three state outputs Data control for upper and lower bytes TEMPERATURE OFFERINGS: Option A1: -40°C to +85°C Option A2: -40°C to +105°C Option A3: -40°C to +125°C Lead-free available DESCRIPTION The ISSI IS65WV25616ALL/IS65WV25616BLL are high- speed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS1 is LOW, and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS65WV25616BALL/65WV25616BLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II). FUNCTIONAL BLOCK DIAGRAM A0-A17 VDD GND I/O...