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IS65WV25616DBLL Dataheets PDF



Part Number IS65WV25616DBLL
Manufacturers ISSI
Logo ISSI
Description ULTRA LOW POWER CMOS STATIC SRAM
Datasheet IS65WV25616DBLL DatasheetIS65WV25616DBLL Datasheet (PDF)

IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM MARCH 2015 FEATURES • High-speed access time: 35, 45, 55 ns • CMOS low power operation 30 mW (typical) operating 6 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply 1.65V--2.2V Vdd (IS62WV25616DALL) 2.3V--3.6V Vdd (IS62/65WV25616DBLL) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial an.

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IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM MARCH 2015 FEATURES • High-speed access time: 35, 45, 55 ns • CMOS low power operation 30 mW (typical) operating 6 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply 1.65V--2.2V Vdd (IS62WV25616DALL) 2.3V--3.6V Vdd (IS62/65WV25616DBLL) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and Automotive temperature support • Lead-free available • 2 CS option available DESCRIPTION The ISSI IS62WV25616DALL and IS62/65WV25616DBLL are high-speed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using ISSI's high- performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselcted) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs.The active LOWWrite Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62WV25616DALL and IS62/65WV25616DBLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm). FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT CS2 CS1 OE CONTROL WE CIRCUIT UB LB COLUMN I/O Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. D1 3/10/2015 IS62WV25616DALL/DBLL, IS65WV25616DBLL PIN CONFIGURATIONS 48- ball mini BGA (6mm x 8mm) (Package Code B) 1 23 45 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CSI I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 44-Pin mini TSOP (Type II) (Package Code T) A4 1 A3 2 A2 3 A1 4 A0 5 CS1 6 I/O0 7 I/O1 8 I/O2 9 I/O3 10 VDD 11 GND 12 I/O4 13 I/O5 14 I/O6 15 I/O7 16 WE 17 A16 18 A15 19 A14 20 A13 21 A12 22 44 A5 43 A6 42 A7 41 OE 40 UB 39 LB 38 I/O15 37 I/O14 36 I/O13 35 I/O12 34 GND 33 VDD 32 I/O11 31 I/O10 30 I/O9 29 I/O8 28 NC 27 A8 26 A9 25 A10 24 A11 23 A17 PIN DESCRIPTIONS A0-A17 I/O0-I/O15 CS1, CS2 OE WE LB UB NC Vdd GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 48-Pin mini BGA (6mm x 8mm)* 2 CS Option (Package Code B2) 1 23 45 6 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC *Available upon request 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015 IS62WV25616DALL/DBLL, IS65WV25616DBLL TRUTH TABLE I/O PIN Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 Vdd Current Not Selected XHXXXX X X L X X X XXXXHH High-Z High-Z High-Z High-Z High-Z High-Z Isb1, Isb2 Isb1, Isb2 Isb1, Isb2 Output Disabled H L H H L X H L H H X L High-Z High-Z Icc High-Z High-Z Icc Read H L H L L H Dout High-Z Icc H L H L H L High-Z Dout H L H L L L Dout Dout Write L L H X L H Din High-Z Icc L L H X H L High-Z Din L L H X L L Din Din ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit Vterm Terminal Voltage with Respect to GND –0.5 to Vdd + 0.5 V Vdd Vdd Rel.


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