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IS65WV6416DALL Dataheets PDF



Part Number IS65WV6416DALL
Manufacturers ISSI
Logo ISSI
Description ULTRA LOW POWER CMOS STATIC RAM
Datasheet IS65WV6416DALL DatasheetIS65WV6416DALL Datasheet (PDF)

IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2012 FEATURES • High-speed access time: 35ns, 45ns, 55ns • CMOS low power operation: 15 mW (typical) operating 1.5 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply 1.65V--2.2V Vdd (62WV6416DALL) 2.3V--3.6V Vdd (65WV6416DBLL) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and .

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IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2012 FEATURES • High-speed access time: 35ns, 45ns, 55ns • CMOS low power operation: 15 mW (typical) operating 1.5 µW (typical) CMOS standby • TTL compatible interface levels • Single power supply 1.65V--2.2V Vdd (62WV6416DALL) 2.3V--3.6V Vdd (65WV6416DBLL) • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial and automotive temperature support • 2CS Option Available • Lead-free available FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The ISSI IS62/65WV6416DALL and IS62/65WV6416DBLL are high-speed, 1M bit static RAMs organized as 64K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62/65WV6416DALL and IS62/65WV6416DBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). A0-A15 DECODER VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS2 CS1 OE WE UB LB I/O DATA CIRCUIT CONTROL CIRCUIT 64K x 16 MEMORY ARRAY COLUMN I/O Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL PIN CONFIGURATIONS 48-Pin mini BGA (6mm x 8mm) (Package Code B) 1 23 45 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CSI I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2) 1 23 45 6 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC PIN DESCRIPTIONS A0-A15 Address Inputs I/O0-I/O15 CS1, CS2 OE WE LB UB Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground 44-Pin mini TSOP (Type II) (Package Code T) A4 1 A3 2 A2 3 A1 4 A0 5 CS1 6 I/O0 7 I/O1 8 I/O2 9 I/O3 10 VDD 11 GND 12 I/O4 13 I/O5 14 I/O6 15 I/O7 16 WE 17 A15 18 A14 19 A13 20 A12 21 NC 22 44 A5 43 A6 42 A7 41 OE 40 UB 39 LB 38 I/O15 37 I/O14 36 I/O13 35 I/O12 34 GND 33 VDD 32 I/.


IS62WV6416DBLL IS65WV6416DALL IS65WV6416DBLL


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