18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDPB41M18A/A1/A2 IS61QDPB451236A/A1/A2
1Mx18, 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)...
Description
IS61QDPB41M18A/A1/A2 IS61QDPB451236A/A1/A2
1Mx18, 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
NOVEMBER 2014
FEATURES
DESCRIPTION
512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and
write input ports.
2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support.
The 18Mb IS61QDPB451236A/A1/A2 and IS61QDPB41M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
The following are registered internally on the rising edge of the K clock:
Read/write address
Read enable
Data Valid Pin (QVLD).
Write enable
+1.8V c...
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