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IS61QDPB41M36B1 Dataheets PDF



Part Number IS61QDPB41M36B1
Manufacturers ISSI
Logo ISSI
Description 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
Datasheet IS61QDPB41M36B1 DatasheetIS61QDPB41M36B1 Datasheet (PDF)

IS61QDPB42M18B/B1/B2 IS61QDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  F.

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IS61QDPB42M18B/B1/B2 IS61QDPB41M36B/B1/B2 2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.  HSTL input and output levels.  Registered addresses, write and read controls, byte writes, data in, and data outputs.  Full data coherency.  Boundary scan using limited set of JTAG 1149.1 functions.  Byte write capability.  Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array  Programmable impedance output drivers via 5x user-supplied precision resistor.  ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#.  The end of top mark (B/B1/B2) is to define options. IS61QDPB41M36B : Don’t care ODT function and pin connection IS61QDPB41M36B1 : Option1 IS61QDPB41M36B2 : Option2 Refer to more detail description at page 6 for each ODT option. The 36Mb IS61QDPB41M36B/B1/B2 and IS61QDPB42M18B/B1/B2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are selftimed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:  Read/write address  Read enable  Write enable  Byte writes for burst addresses 1 and 3  Data-in for burst addresses 1 and 3 The following are registered on the rising edge of the K# clock:  Byte writes for burst addresses 2 and 4  Data-in for burst addresses 2 and 4 Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. Two full clock cycles are required to complete a write operation. During the burst read operation, the data-outs from the first and third bursts are updated from output registers of the third and fourth rising edges of the K# clock (starting 2.5 cycles later after read command). The data-outs from the second and fourth bursts are updated with the fourth and fifth rising edges of the K clock where the read command receives at the first rising edge of K. Two full clock cycles are required to complete a read operation. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. B 10/14/2014 1 IS61QDPB42M18B/B1/B2 IS61QDPB41M36B/B1/B2 Package ballout and description x36 FBGA Ball ballout (Top View) 1234 A CQ# NC/SA1 NC/SA1 W# B Q27 Q18 D18 SA C D27 Q28 D19 VSS D D28 D20 Q19 VSS E Q29 D29 Q20 VDDQ F Q30 Q21 D21 VDDQ G D30 D22 Q22 VDDQ H Doff# VREF VDDQ VDDQ J D31 Q31 D23 VDDQ K Q32 D32 Q23 .


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