72Mb QUADP SYNCHRONOUS SRAM
IS61QDPB44M18B/B1/B2 IS61QDPB42M36B/B1/B2
4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
D...
Description
IS61QDPB44M18B/B1/B2 IS61QDPB42M36B/B1/B2
4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
DECEMBER 2015
FEATURES 2Mx36 and 4Mx18 configuration available.
On-chip Delay Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
Data Valid Pin (QVLD).
+1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability. Fine ball grid array (FBGA) package
13mm x 15mm & 15mm x 17mm body size 165-ball (11 x 15) array
Programmable impedance output drivers via 5x user-supplied precision resistor.
DESCRIPTION The 72Mb IS61QDPB42M36B/B1/B2 and IS61QDPB44M18B/B1/B2 are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates...
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