IS61QDB22M18

36 Mb (1M x 36. & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs I Features 1M x 36 or 2M x 18. On-chip delay-locked loop (DLL) for wide data valid window. Separate read and write ports with concurrent read and write operations. Synchronous pipeline read with early write operation. Double data rate (DDR) interface for read and write input ports. Fixed 2-bit burst for read and write operations. Clock stop support. Two input clocks (K and K) for address and control registering at rising edges only. Two input clocks (C and C) for data output control. JANUARY 2010 Two echo clocks (CQ and CQ) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. HSTL input and output levels. Registered addresses, write and read controls, byte writes, data in, and data outputs. Full data coherency. Boundary scan using limited set of JTAG 1149.1 functions. Byte write capability. Fine ball grid array (FBGA) package - 15mm x 17mm body size - 1mm pitch - 165-ball (11 x 15) array Programmable impedance output drivers via 5x user-supplied precision resistor. Description The 36Mb IS61QDB21Mx36 and IS61QDB22Mx18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing R...