Document
IS61QDB24M18A IS61QDB22M36A
4Mx18, 2Mx36 72Mb QUAD (Burst 2) Synchronous SRAM
AUGUST 2014
FEATURES
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations. Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two output clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
+1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability. Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array Programmable impedance output drivers via 5x user-supplied precision resistor.
DESCRIPTION
The and are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
all internal operations are self-timed. Refer to the
for a description of the
basic operations of these
SRAMs.
The input address bus operates at double data rate. The following are registered internally on the rising edge of the K clock:
Read address
Read enable
Write enable
Byte writes
Data-in for early writes
The following are registered on the rising edge of the K# clock:
Write address
Byte writes
Data-in for second burst addresses
Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered half a cycle earlier than the write address. The first data-in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the K# clock.
During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the C# clock (starting 1.5 cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the C clock. The K and K# clocks are used to time the data-outs whenever the C and C# clocks are tied high.
The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com Rev. A 8/7/2014
1
IS61QDB24M18A IS61QDB22M36A
Package ballout and description
x36 FBGA Ball Configuration (Top View)
123 A CQ# NC/SA1 SA
45678 W# BW2# K# BW1# R#
B Q27 Q18 D18
SA BW3#
K
BW0#
SA
C D27 Q28 D19 VSS SA SA SA VSS
D D28 D20 Q19 VSS VSS VSS VSS VSS
E Q29 D29 Q20 VDDQ VSS
VSS
VSS
VDDQ
F Q30 Q21 D21 VDDQ VDD
VSS
VDD
VDDQ
G D30 D22 Q22 VDDQ VDD
VSS
VDD
VDDQ
H Doff# VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J D31 Q31 D23 VDDQ VDD
VSS
VDD
VDDQ
K Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
L Q33 Q24 D24 VDDQ VSS
VSS
VSS
VDDQ
M D33 Q34 D25 VSS VSS VSS VSS VSS
N D34 D26 Q25 VSS SA SA SA VSS
P Q35 D35 Q26
SA
SA
C
SA SA
R TDO TCK
SA
SA
SA
C#
SA
SA
Notes: The following balls are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb.
9 SA D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA
10 NC/SA1
Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS
11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
x18 FBGA Ball Configuration (Top View)
123 A CQ# NC/SA1 SA
45678 W# BW1# K# NC/SA1 R#
B NC
Q9
D9 SA NC
K
BW0.