18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
IS61QDB41M18A IS61QDB451236A
1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
FEATURES
DESCRIPTION
OCTOBER 2014
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Description
IS61QDB41M18A IS61QDB451236A
1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
FEATURES
DESCRIPTION
OCTOBER 2014
512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked loop (DLL) for wide data valid
window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and write input ports.
1.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support. Two input clocks (K and K#) for address and control
registering at rising edges only.
Two output clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
+1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability.
Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
Programmable impedance output drivers via 5x user-supplied precision resistor.
The 18Mb IS61QDB451236A and IS61QDB41M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write ...
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