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IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2
1Mx18 , 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.0 Cycle Read Latency)
OCTOBER 2014
FEATURES
DESCRIPTION
512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and
write input ports.
2.0 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support.
The 18Mb IS61QDP2B451236A/A1/A2 and IS61QDP2B41M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
The following are registered internally on the rising edge of the K clock:
Read/write address
Read enable
Data Valid Pin (QVLD).
Write enable
+1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs.
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3
The following are registered on the rising edge of the K# clock:
Byte writes for burst addresses 2 and 4
Full data coherency.
Data-in for burst addresses 2 and 4
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array Programmable impedance output drivers via 5x user-supplied precision resistor.
Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. Two full clock cycles are required to complete a write operation.
ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options. IS61QDP2B451236A : Don’t care ODT function and pin connection
IS61QDP2B451236A1 : Option1
IS61QDP2B451236A2 : Option2
During the burst read operation, the data-outs from the first and third bursts are updated from output.