36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2
2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.0 Cycle Read Latency)
...
Description
IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2
2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.0 Cycle Read Latency)
JANUARY 2015
FEATURES
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.0 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
Data Valid Pin (QVLD).
+1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
DESCRIPTION
The 36Mb IS61QDP2B41M36A/A1/A2 and IS61QDP2B42M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate.
The following are registered internally on the rising edge of the K clo...
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