MS90C386B

MS90C386B MS90C386B ——+3.3V 175MHz 24bits COLOR LVDS Receiver General Description The MS90C386B receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The MS90C386B converts the LVDS data streams back into 28bits of CMOS/TTL data with the choice of the rising edge or falling edge clock for the convenience with a variety of LCD panel controllers. At a transmit clock frequency of 175Mhz, 24bits of GRB data and 4bits of timing and control data (HSYNC,VSYCN,DE,CNTL) are transmitted at an effective rate of 1225Mbps per LVDS channel. Using a 175MHz clock, the data throughput is 612.5Mbytes/sec. Features  Clock range：20-175MHz  Narrow bus reduces cable size  Single 3.3V supply  Power-down Mode  Supports VGA、SVGA、XGA、SXGA  Up to 4.9Gbps throughput  Up to 612.5Megabytes/sec bandwidth  PLL requires no external components  Compatible with TIA/EIA-644 LVDS standard  TSSOP56 Package Hangzhou Ruimeng Technology Co.,LTD Http: www.relmon.com -- 1 - - Pin Diagram MS90C386B Pin Description Pin Name RxIN0+,RxIN0RxIN1+, RxIN1RxIN2+, RxIN2RxIN3+, RxIN3RxCLKIN+, RxCLKIN- Pin No. 10, 9 12, 11 16, 15 20, 19 18, 17 RxOUT0 ~ RxOUT6 RxOUT7 ~ RxOUT13 RxOUT14 ~ RxOUT20 RxOUT21 ~ RxOUT27 RxCLKOUT PDN 27,29,30,32,33, 34,35 37,38,39,41,42, 43,45 46,47,49,50,51, 53,54 55,1,2,3,5,6,7 26 25 Vcc GND LVDS Vcc LVDS GND PLL Vcc 31,40,48,56 28,36,44,52,4 13 8,14,21 23 I/O LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT O...