Document
Data Sheet
FEATURES
Supports data rates from dc up to 32 Gbps Protocol and data rate agnostic Low latency (<170 ps) Integrated AGC with differential sensitivity of <50 mV Up to 20 dB programmable multiple unit interval input
equalization Extended chromatic and polarization mode dispersion
tolerance Programmable differential output amplitude control of up to
600 mV Single 3.3 V supply eliminating external regulators Wide temperature range from −40°C to +95°C 5 mm × 5 mm, 32-lead LFCSP package
APPLICATIONS
40 Gbps/100 Gbps DQPSK direct detection receivers Short and long reach CFP2 and QSFP+ modules CEI-28G MR and CEI-25G LR 100 GE line cards 16 Gbps and 32 Gbps Fibre Channel Infiniband 14 Gbps FDR and 28 Gbps EDR rates Signal conditioning for backplane and line cards Broadband test and measurement equipment
GENERAL DESCRIPTION
The HMC6545 is a low power, high performance, fully programmable, dual-channel, asynchronous advanced linear equalizer that operates at data rates of up to 32 Gbps. The HMC6545 is protocol and data rate agnostic, and it can operate on the transmit path to predistort a transmitted signal to invert channel distortion or on the receiver path to equalize the distorted and attenuated received signal. The HMC6545 is effective in dealing with chromatic and polarization mode dispersion and intersymbol interference (ISI) caused by a wide variety of transmission media (backplane or fiber) and channel lengths.
The HMC6545 consists of an automatic gain control (AGC); dc offset correction circuitry; a 9-tap, 18 ps spaced feedforward equalizer (FFE); a summing node; and a linear programmable output driver. The input AGC linearly attenuates or amplifies the distorted input signal to generate a constant voltage at the
32 Gbps, Dual Channel, Advanced Linear Equalizer
HMC6545
FUNCTIONAL BLOCK DIAGRAM
32 CAGC0 31 VCC0 30 COMPP0 29 COMPN0 28 RST 27 REGSEL1 26 REGSEL0 25 VCC0
GND 1 INP0 2 INN0 3 GND 4 GND 5 INP1 6 INN1 7 GND 8
HMC6545
AGC
T/2 T/2 T/2 T/2
LPF
AGC LPF
c0 c1 c2 cn Σ
SERIAL CONTROL REGISTERS
T/2 T/2 T/2 T/2 d0 d1 d2 dn
Σ
Figure 1.
24 GND 23 OUTP0 22 OUTN0 21 GND 20 GND 19 OUTP1 18 OUTN1 17 GND
PACKAGE BASE GND
CAGC1 9 VCC1 10
COMPP1 11 COMPN1 12
SDA 13 SCL 14 SVCC 15 VCC1 16
13393-001
input of the FFE. The 9-tap FFE is programmed via 2-wire interface to generate wide range frequency responses that are precursor or postcursor in nature for compensating signal impairments. After FFE tap coefficients are summed at the summing node, the signal is received by a linear output driver. DC offset correction circuitry is controlled either automatically or manually via Forward Error Correction (FEC).
All high speed differential inputs and outputs of the HMC6545 are current mode logic (CML) and terminated on chip with 50 Ω to the positive supply, 3.3 V, and can be dc-coupled or ac-coupled. The inputs and outputs of the HMC6545 can be operated either differentially or single-ended. The low power, high performance, and feature rich HMC6545 is packaged in a 5 mm × 5 mm, 32-lead LFCSP package. The device uses a single 3.3 V supply, eliminating external regulators. The HMC6545 operates over a −40°C to +95°C temperature range.
Rev. B
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HMC6545
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3
DC Electrical Characteristics...................................................... 3 AC Electrical Characteristics ...................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Interface Schematics..............................