ADSP-SC583

SHARC+ Dual-Core DSP with Arm Cortex-A5 ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587 SYSTEM FEATURES Dual enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short-word, word, long-word addressed Arm Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache/32 kB L1 data cache 256 kB Level 2 (L2) cache with parity Powerful DMA system On-chip memory protection Integrated safety features 19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant Low system power across automotive temperature range MEMORY Large on-chip L2 SRAM with ECC protection, up to 256 kB On-chip L2 ROM (512 kB) Two Level 3 (L3) interfaces optimized for low system power, providing a 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices ADDITIONAL FEATURES Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for Arm TrustZone Accelerators High performance pipelined FFT/IFFT engine FIR, IIR, HAE, SINC offload engines AEC-Q100 qualified for automotive applications SYSTEM CONTROL SECURITY AND PROTECTION SYSTEM PROTECTION (SPU) SYSTEM MEMORY PROTECTION UNIT (SMPU) FAULT MANAGEMENT Arm® TrustZone® SECURITY DUAL CRC WATCHDOGS OTP MEMORY THERMAL MONITOR UNIT (TMU) PROGRAM...